NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 388 / 1325

SCG_SIRCCSR field descriptions (continued)
Field Description
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–4
Reserved
This field is reserved and is always has the value 0
This field is reserved.
3
Reserved
This field is reserved and is always has the value 0
This field is reserved.
This read-only field is reserved and always has the value 0.
2
SIRCLPEN
Slow IRC Low Power Enable
0 Slow IRC is disabled in VLP modes
1 Slow IRC is enabled in VLP modes
1
SIRCSTEN
Slow IRC Stop Enable
0 Slow IRC is disabled in supported Stop modes
1 Slow IRC is enabled in supported Stop modes
0
SIRCEN
Slow IRC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 Slow IRC is disabled
1 Slow IRC is enabled
18.3.11 Slow IRC Divide Register (SCG_SIRCDIV)
To prevent glitches to the output divided clock, change SIRDIV when the Slow IRC is
disabled.
Address: 4006_4000h base + 204h offset = 4006_4204h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
Reserved
0 SIRCDIV
2
0 SIRCDIV
1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SIRCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
SIRCDIV2
Slow IRC Clock Divide 2
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
388 NXP Semiconductors