NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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SCG_FIRCDIV field descriptions (continued)
Field Description
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
18.3.15 Fast IRC Configuration Register (SCG_FIRCCFG)
The FIRCCFG register cannot be changed when the Fast IRC is enabled. When the Fast
IRC is enabled, writes to this register are ignored, and there is no transfer error.
Address: 4006_4000h base + 308h offset = 4006_4308h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RANGE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_FIRCCFG field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
RANGE Frequency Range
See chip-specific information for supported frequency ranges.
00 Fast IRC is trimmed to 48 MHz
01 Fast IRC is trimmed to 52 MHz
10 Fast IRC is trimmed to 56 MHz
11 Fast IRC is trimmed to 60 MHz
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 393