NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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SCG_PARAM field descriptions
Field Description
31–27
DIVPRES
Divider Present
Indicates which system clock dividers are present in this instance of SCG.
DIVPRES[27]=1 System DIVSLOW is present.
DIVPRES[31]=1 System DIVCORE is present
26–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CLKPRES Clock Present
Indicates which clock sources are present in this instance of SCG. Any bits not defined in this bit field are
Reserved and always has the value 0 when read.
CLKPRES[0] Reserved
CLKPRES[1]=1System OSC (SOSC) is present
CLKPRES[2]=1Slow IRC (SIRC) is present
CLKPRES[3]=1Fast IRC (FIRC) is present
CLKPRES[5]=1Low Power FLL (LPFLL) is present
18.3.3 Clock Status Register (SCG_CSR)
This register returns the currently configured system clock source and the system clock
dividers for the core (DIVCORE) and peripheral interface clock (DIVSLOW). The
SCG_CSR reflects the configuration set by one of three clock control registers
SCG_RCCR, SCG_VCCR.
Note: Writing to this register will result in a transfer error.
Address: 4006_4000h base + 10h offset = 4006_4010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 SCS 0 DIVCORE 0 0 0 DIVSLOW
W
Reset
0 0 0 0 0 0 1 1 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* Notes:
DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The valid reset values are
div-by-1 or div-by-2 when resetting into RUN mode or div-by-4 or div-by-8 when resetting into VLPR mode.
•
SCG_CSR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 375