Freescale Semiconductor MPC5565, Справочное руководство

Страница: 864 / 1153

Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-41
Figure 19-19 shows the DSI serialization logic.
Figure 19-19. DSI Serialization Diagram
19.4.4.4 DSI Deserialization
When all bits in a DSI frame have been shifted in, the frame is copied to the DSPI x _DDR. This register
presents the deserialized data as parallel output signal values. The DSPI x _DDR is memory mapped to
allow host software to read the deserialized data directly. Figure 19-20 shows the DSI deserialization logic.
for more information on the DSPI x _DDR.
Refer to Section 19.3.2.14, “DSPI DSI Deserialization Data Register (DSPIx_DDR) .”
Figure 19-20. DSI Deserialization Diagram
19.4.4.5 DSI Transfer Initiation Control
Data transfers for a master DSPI in DSI configuration are initiated by a condition. When chaining DSPIs,
the master and all slaves must be configured for the transfer initiation. The transfer initiation conditions
are selected by the TRRE and CID bits in the DSPI
x _DSICR.
1
0
DSPI alternate
serialization data register
SOUT x
Parallel
DSI configuration
register
DSI transmit
comparison register
Clock
logic
0 1 • • • • • 15
Shift register DSI serialization
data register
Control
logic
SCK x
inputs
PCS x
ht
16
16
16
16
TXSS
Slave bus interface
16
SIN
Control
logic
0 1 • • • • • 15
Shift register
16
Slave bus interface
Parallel DSI deserialization
data register outputs
16