Freescale Semiconductor MPC5565, Справочное руководство

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Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 21-5
21.2.2 Detailed Signal Description
21.2.2.1 CNRX x
This pin is the receive pin to the CAN bus transceiver. The dominant state is represented by logic level 0.
The recessive state is represented by logic level 1.
21.2.2.2 CNTX x
This pin is the transmit pin to the CAN bus transceiver. The dominant state is represented by logic level 0.
The recessive state is represented by logic level 1.
21.3 Memory Map/Register Definition
This section describes the registers and data structures in the FlexCAN2 module. The addresses presented
here are relative to the base address of the module.
The address space occupied by FlexCAN2 is continuous: 128 bytes for registers starting at the module base
address, extra space for MB storage, and 1024 bytes for 64 MBs.
21.3.1 Memory Map
The complete memory map for a FlexCAN2 module with its 64 MBs is shown in Table 21-2 . Except for
the base addresses, the three FlexCAN2 modules have identical memory maps. Each individual register is
identified by its complete name and the corresponding mnemonic.
Table 21-1. FlexCAN2 Signals
Signal Name
1
1
x i ndicates FlexCAN2 module A, B, or C.
Direction Description
CNRX x I CAN receive
CNTX x O CAN transmit
Table 21-2. Module Memory Map
Address Register Name Register Description Bits
Base = 0xFFFC_0000 (FlexCAN A)
Base = 0xFFFC_4000 (FlexCAN B)
Base = 0xFFFC_8000 (FlexCAN C) CAN x _MCR Module configuration register 32
Base + 0x0004 CAN x _CR Control register 32
Base + 0x0008 CAN x _TIMER Free running timer 32
Base + 0x000C — Reserved —
Base + 0x0010 CAN x _RXGMASK RX global mask 32
Base + 0x0014 CAN x _RX14MASK RX buffer 14 mask 32
Base + 0x0018 CAN x _RX15MASK RX buffer 15 mask 32