Freescale Semiconductor MPC5565, Справочное руководство

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-51
Write Configuration Command Message Format for On-Chip ADC Operation
Figure 18-27 describes the command message format for a write configuration command when interfacing
with the on-chip ADCs. A write configuration command is used to set the control registers of the on-chip
ADCs. No conversion data is returned for a write configuration command. Write configuration commands
are differentiated from read configuration commands by a negated R/W bit.
16–23
CHANNEL_
NUMBER
[0:7]
Channel number. Selects the analog input channel. The software programs this field with the channel number
corresponding to the analog input pin to be sampled and converted. Refer to
Section 18.4.6.1, “Channel
Assignment ,” for details.
24–31 Reserved.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EOQ PAUSE Reserved
EB
(0b0)
BN
R/W
(0b0)
ADC_REGISTER HIGH BYTE
CFIFO Header ADC Command
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADC_REGISTER LOW BYTE ADC_REG_ADDRESS
ADC Command
Figure 18-27. Write Configuration Command Message Format for On-chip ADC Operation
Table 18-35. On-Chip ADC Field Descriptions: Write Configuration
Field Description
0
EOQ
End-of-queue. Asserted in the last command of a command queue to indicate to the eQADC that a scan of the
queue is completed. EOQ instructs the eQADC to reset its current CFIFO transfer counter value (TC_CF) to 0.
Depending on the CFIFO mode of operation, the CFIFO status also changes upon the detection of an asserted
EOQ bit on the last transferred command. Refer to
Section 18.4.3.5, “CFIFO Scan Trigger Modes ,” for details.
0 Not the last entry of the command queue.
1 Last entry of the command queue.
Note: If both the pause and EOQ bits are asserted in the same command message the respective flags are set,
but the CFIFO status changes as if only the EOQ bit were asserted.
1
PAUSE
Pause bit. Allows software to create sub-queues within a command queue. When the eQADC completes the
transfer of a command with an asserted pause bit, the CFIFO enters the WAITING FOR TRIGGER state. Refer
to
Section 18.4.3.6.1, “CFIFO Operation Status ,” for a description of the state transitions. The pause bit is only
valid when CFIFO operation mode is configured to single or continuous-scan edge trigger mode.
0 Do not enter WAITING FOR TRIGGER state after transfer of the current command message.
1 Enter WAITING FOR TRIGGER state after transfer of the current command message.
Note: If both the pause and EOQ bits are asserted in the same command message, the respective flags are set,
but the CFIFO status changes as if only the EOQ bit were asserted.
2–4 Reserved.
Table 18-34. On-Chip ADC Field Descriptions: Conversion Command Message Format (continued)
Field Description