Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-26
Freescale Semiconductor
12
RFOF
n
RFIFO overflow flag
n
. Indicates an overflow event on RFIFO
n
. RFOF
n
is set when RFIFO
n
is already full, and a
new data is received from the on-chip ADCs or from the external device. The RFIFO
n
does not overwrite older data
in the RFIFO, and the new data is ignored. When RFOIE
n
(see
Section 18.3.2.7, “eQADC Interrupt and eDMA
Control Registers 0–5 (EQADC_IDCRn)
”) and RFOF
n
are both asserted, the eQADC generates an interrupt
request.
Apart from generating an independent interrupt request for an RFIFO
n
overflow event, the eQADC also provides a
combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt, and the
command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIE
n
, CFUIE
n
, and TORIE
n
are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOF
n
, CFUF
n
, and TORF
n
(assuming that all interrupts are enabled). Refer to
,” for details.
Write 1 to clear RFOF
n
. Writing a 0 has no effect.
0 No RFIFO overflow event occurred.
1 An RFIFO overflow event occurred.
13
Reserved.
14
RFDF
n
RFIFO drain flag
n
. Indicates if RFIFO
n
has valid entries that can be drained or not. RFDF
n
is set when the RFIFO
n
has at least one valid entry in it. When RFDE
n
(see
Section 18.3.2.7, “eQADC Interrupt and eDMA Control Registers
”) and RFDF
n
are both asserted, an interrupt or an eDMA request is generated depending on
the status of the RFDS
n
bit. When RFDS
n
is negated (interrupt requests selected), software clears RFDF
n
by writing
a 1 to it. Writing a 0 has no effect. When RFDS
n
is asserted (eDMA requests selected), RFDF
n
is automatically
cleared by the eQADC when the RFIFO becomes empty.
0 RFIFO
n
is empty.
1 RFIFO
n
has at least one valid entry.
Note:
In the interrupt service routine, RFDF must be cleared only after the RFIFO
n
pop register is read.
Note:
RFDF
n
should not be cleared when RFDS
n
is asserted (eDMA requests selected).
15
Reserved.
16–19
CFCTR
n
[0:3]
CFIFO
n
entry counter. Indicates the number of commands stored in the CFIFO
n
. When the eQADC completes
transferring a piece of new data from the CFIFO
n
, it decrements CFCTR
n
by 1. Writing a word or any bytes to the
corresponding CFIFO Push Register (see
Section 18.3.2.4, “eQADC CFIFO Push Registers 0–5
”) increments CFCTR
n
by 1. Writing any value to CFCTR
n
has no effect.
20–23
TNX
TPTR
n
[0:3]
CFIFO
n
transfer next pointer. Indicates the index of the next entry to be removed from CFIFO
n
when it completes a
transfer. When TNXTPTR
n
is 0, it points to the entry with the smallest memory-mapped address inside CFIFO
n
.
TNXTPTR
n
is only updated when a command transfer is completed. If the maximum index number (CFIFO depth
minus 1) is reached, TNXTPTR
n
is wrapped to 0, else, it is incremented by 1. For details refer to
.” Writing any value to TNXTPTR
n
has no effect.
24–27
RFCTR
n
[0:3]
RFIFO
n
entry counter. Indicates the number of data items stored in the RFIFO
n
. When the eQADC stores a piece
of new data into RFIFO
n,
it increments RFCTR
n
by 1. Reading the whole word, halfword or any bytes of the
corresponding Result FIFO pop register (see
Section 18.3.2.5, “eQADC Result FIFO Pop Registers 0–5
”) decrements RFCTR
n
by 1. Writing any value to RFCTR
n
itself has no effect.
28–31
POPNX
TPTR
n
[0:3]
RFIFO
n
pop next pointer. Indicates the index of the entry that is returned when EQADC_RFPR
n
is read. When
POPNXTPTR
n
is 0, it points to the entry with the smallest memory-mapped address inside RFIFO
n
. POPNXTPTR
n
is updated when EQADC_RFPR
n
is read. If the maximum index number (RFIFO depth minus 1) is reached,
POPNXTPTR
n
is wrapped to 0, else, it is incremented by 1. For details refer to
Section 18.4.4.1, “RFIFO Basic
.” Writing any value to POPNXTPTR
n
has no effect.
Table 18-12. EQADC_FISR
n
Field Descriptions (continued)
Field
Description
Содержание MPC5565
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