Interrupt Controller (INTC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
10-19
0x07A0
122
EQADC_FISR4[PF]
eQADC command FIFO 4 pause flag
0x07B0
123
EQADC_FISR4[EOQF]
eQADC command FIFO 4 command queue end-of-queue
flag
0x07C0
124
EQADC_FISR4[CFFF]
eQADC command FIFO 4 fill flag
0x07D0
125
EQADC_FISR4[RFDF]
eQADC receive FIFO 4 drain flag
0x07E0
126
EQADC_FISR5[NCF]
eQADC command FIFO 5 non-coherency flag
0x07F0
127
EQADC_FISR5[PF]
eQADC command FIFO 5 pause flag
0x0800
128
EQADC_FISR5[EOQF]
eQADC command FIFO 5 command queue end-of-queue
flag
0x0810
129
EQADC_FISR5[CFFF]
eQADC command FIFO 5 fill flag
0x0820
130
EQADC_FISR5[RFDF]
eQADC receive FIFO 5 drain flag
DSPI B, DSPI C, DSPI D
0x0830
131
DSPI_BSR[TFUF]
DSPI_BSR[RFOF]
DSPI B combined overrun interrupt requests:
• Transmit FIFO underflow
• Receive FIFO overflow
0x0840
132
DSPI_BSR[EOQF]
DSPI B transmit FIFO end-of-queue flag
0x0850
133
DSPI_BSR[TFFF]
DSPI B transfer complete
0x0860
134
DSPI_BSR[TCF]
DSPI B Rx FIFO drain request
0x0870
135
DSPI_BSR[RFDF]
DSPI B Tx FIFO fill request
0x0880
136
DSPI_CSR[TFUF]
DSPI_CSR[RFOF]
DSPI C combined overrun interrupt requests:
• Transmit FIFO underflow
• Receive FIFO overflow
0x0890
137
DSPI_CSR[EOQF]
DSPI C transmit FIFO end-of-queue flag
0x08A0
138
DSPI_CSR[TFFF]
DSPI C transfer complete
0x08B0
139
DSPI_CSR[TCF]
DSPI C Rx FIFO drain request
0x08C0
140
DSPI_CSR[RFDF]
DSPI C Tx FIFO fill request
0x08D0
141
DSPI_DSR[TFUF]
DSPI_DSR[RFOF]
DSPI D combined overrun interrupt requests:
• Transmit FIFO underflow
• Receive FIFO overflow
0x08E0
142
DSPI_DSR[EOQF]
DSPI D transmit FIFO end-of-queue flag
0x08F0
143
DSPI_DSR[TFFF]
DSPI D transfer complete
0x0900
144
DSPI_DSR[TCF]
DSPI D Rx FIFO drain request
0x0910
145
DSPI_DSR[RFDF]
DSPI D Tx FIFO fill request
Table 10-9. MPC5565 Interrupt Request Sources (continued)
Hardware
Vector Mode
Offset
Vector
Number
1
Source
2
Description
Содержание MPC5565
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