Freescale Semiconductor MPC5565, Справочное руководство

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
11-24 Freescale Semiconductor
The FMPLL remains in SCM until the next reset. Note that when the FMPLL is operated in SCM, writes
to FMPLL_SYNCR[RFD] have no effect on clock frequency. The SCM system frequency stated in the
device
Data Sheet assumes that the RFD has been programmed to 0x0.
If loss of clock is enabled and the loss-of-clock is due to a FMPLL failure (for example, loss of feedback
clock), the FMPLL reference becomes the system clock’s source until the next reset, even if the FMPLL
regains itself and re-locks.
A special loss of clock condition occurs when both the reference and the FMPLL fail. The failures can be
simultaneous or the FMPLL can fail first. In either case, the reference clock failure takes priority and the
FMPLL attempts to operate in SCM. If successful, the FMPLL remains in SCM until the next reset. During
SCM, modulation is always disabled. If the FMPLL cannot operate in SCM, the system remains static until
the next reset. Both the reference and the FMPLL must be functioning properly to exit reset.
11.4.2.6.2 Loss-of-Clock Reset
When a loss of clock condition is recognized, reset is asserted if the FMPLL_SYNCR[LOCRE] bit is set.
The LOCF and LOC bits in FMPLL_SYNSR are cleared after reset, therefore, the SIU_RSR must be read
to determine that a loss of clock condition occurred. LOCRE has no effect in bypass mode.
To exit reset in FMPLLmode, the reference must be present and the FMPLL must acquire lock.
11.4.2.6.3 Loss-of-Clock Interrupt Request
When a loss of clock condition is recognized, the FMPLL requests an interrupt if the
FMPLL_SYNCR[LOCIRQ] bit is set. The LOCIRQ bit has no effect in bypass mode or if
FMPLL_SYNCR[LOCEN] = 0.
11.4.3 Clock Configuration
In crystal reference and external reference clock mode, the default system frequency is determined by the
MFD, RFD, and PREDIV reset values. Refer to Section 11.3.1.1, “Synthesizer Control Register
(FMPLL_SYNCR) .” The frequency multiplier is determined by the RFD, PREDIV, and multiplication
frequency divisor (MFD) bits in FMPLL_SYNCR.
Table 11-9 shows the clock-out to clock-in frequency relationships for the possible clock modes.
Table 11-8. Loss of Clock Summary
Clock Mode
System Clock
Source before
Failure
REFERENCE FAILURE
Alternate Clock Selected by LOC
Circuitry until Reset
PLL FAILURE
Alternate Clock Selected by LOC
Circuitry until Reset
Crystal Reference
External Reference PLL PLL self-clocked mode PLL reference
Bypass External clock(s) None N/A