External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
12-3
Figure 12-1. MPC5565 EBI Connections
12.1.2
Overview
The EBI includes a memory controller that generates interface signals to support a variety of external
memories. This includes single data rate (SDR) burst mode flash, external SRAM, and asynchronous
memories. It supports up to four regions (via chip selects), each with its own programmed attributes.
External Bus
Interface
Memory
controller
External master
controller
Bus
monitor
Registers
Slave
interface/
CLKOUT driver
CLKOUT
crossbar switch
(XBAR)
Master
interface/
crossbar switch
(XBAR)
Peripheral
bridge
CS[0:3]
1
TS
OE
BDIP
TA
TEA
1
WE/BE[0:3]
1
(PBridge A)
system bus
system bus
DATA[0:31]
1
RD_WR
CAL_CS[0, 2:3]
CAL_TS
CAL_OE
CAL_WE/BE[0:1]
CAL_RD_WR
CAL_DATA[0:15]
CAL_ADDR[10:30]
2
ADDR[12:31]
1
Arbiter
1
Although the MPC5565 is designed to support a 32-bit EBI, not all pins are available on the 324 package.
Refer to
for a description of the differences between the device design and package pinouts.
2
The MPC5565 calibration bus and calibration signals are only available on the VertiCal assembly.
Available on the VertiCAL
only.
assembly
Содержание MPC5565
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