EXFO Power Blazer 88200NGE, User Manual

Page: 177 / 887

Test Setup - Test Configurator, Timer, and System
Power Blazer
167
Clock
Clock
Allows the configuration of the clock synchronization.
From the Test menu, tap Setup , Test Configurator , and tap on the clock
block.
Note: A TA-Sync transceiver system is required on the 88260 module when using
an external clock input or when generating an external clock out. In this
case a message is displayed when there is an issue with the TA-Sync (see
Transceiver System Status
on page 116).
Clock Synchronization
Clock Mode
allows selecting the clock source that will be used for
transmission (TX).

Internal
: Internal clock of the unit (STRATUM 3). The clock mode
is forced to Internal for Multi-Channel OTN and for eCPRI BERT in
Round-Trip or One-Way P<m>  P<m> Latency mode.

Recovered : Line clock from the input port signal involved in the
test. Available with Transport test applications, CPRI/OBSAI RRH,
and Ethernet applications using 10G WAN. The clock mode is
forced to
Recovered
for 1GE electrical interface using
Slave
local
clock (see Local Clock on page 226).

External
: Clock signal from the EXT CLK port. The clock mode is
forced to External for eCPRI BERT in One-way Latency mode
since a 1PPS clock is required.

Backplane : Clock from another module on the platform (only
supported on FTB-2 and FTB-2 Pro platforms). The other module
must support the backplane clock feature and must be enabled.
Not available when the
Backplane Clock
check box is selected
(see page 173). The Backplane clock cannot be shared between
FTB- and FTBx- modules.