NXP Semiconductors MKW01Z128, Reference Manual

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31.3.10 SPI control register 3 (SPIx_C3)
This register introduces a 64-bit FIFO function on both transmit and receive buffers. It
applies only for an instance of the SPI module that supports the FIFO feature.
FIFO mode is enabled by setting the FIFOMODE bit to 1. A write to this register occurs
only when it sets the FIFOMODE bit to 1.
Using this FIFO feature allows the SPI to provide high speed transfers of large amounts
of data without consuming large amounts of the CPU bandwidth.
Enabling this FIFO function affects the behavior of some of the read/write buffer flags in
the S register as follows:
• When the receive FIFO has data in it, S[RFIFOEF] is 0. As a result:
• If C2[RXDMAE] is 1, RFIFOEF_b generates a receive DMA request. The DMA
request remains active until RFIFOEF is set to 1, indicating the receive buffer is
empty.
• If C2[RXDMAE] is 0 and C1[SPIE] is 1, SPRF interrupts the CPU.
• When the transmit FIFO is not full, S[TXFULLF] is 0. As a result:
• If C2[TXDMAE] is 1, TXFULLF_b generates a transmit DMA request. The
DMA request remains active until TXFULLF is set to 1, indicating the transmit
FIFO is full.
• If C2[TXDMAE] is 0 and C1[SPTIE] is 1, SPTEF interrupts the CPU.
Two interrupt enable bits, TNEARIEN and RNFULLIEN, provide CPU interrupts based
on the "watermark" feature of the TNEARF and RNFULLF flags of the S register.
Address: Base a Bh offset
Bit 7 6 5 4 3 2 1 0
Read 0 TNEAREF_
MARK
RNFULLF_
MARK
INTCLR TNEARIEN RNFULLIEN FIFOMODE
Write
Reset 0 0 0 0 0 0 0 0
SPIx_C3 field descriptions
Field Description
7–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
TNEAREF_
MARK
Transmit FIFO nearly empty watermark
This bit selects the mark after which the TNEAREF flag is asserted.
0 TNEAREF is set when the transmit FIFO has 16 bits or less
1 TNEAREF is set when the transmit FIFO has 32 bits or less
Table continues on the next page...
Chapter 31 Serial Peripheral Interface (SPI)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 595