NXP Semiconductors MKW01Z128, Reference Manual

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MKW01Z128 Transceiver - MCU SPI Interface
MKW01xxRM Reference Manual, Rev. 3, 04/2016
8-4 Freescale Semiconductor, Inc.
— The NSS pin goes low at the beginning of the frame and stays low between bytes. It goes high
only after the last byte transfer.
• FIFO access - special case of burst access for the FIFO
— The address byte corresponds to the address of the FIFO
— The address is not automatically incremented, but stays pointed at the FIFO.
— The data bytes are sequentially written to or read from the FIFO.
— The NSS pin goes low at the beginning of the frame and stays low between bytes. It goes high
only after the last byte transfer
For the defined transaction formats:
• The falling edge of NSS always initializes the start of the frame transfer.
• All address and data sent MSB first
• The address byte (first byte) of the transaction is composed of -
— WNR Bit (Bit 7) - which is “1” for write access and “0” for read access
— Address (Bit 6:0) - 7-bit register address (sent MSB first)
• Following data byte(s) -
— Write data sent on MOSI
— Read data sent on MISO
• The rising edge of NSS signifies the end of the frame transfer (NSS must remain asserted for the
entire frame).
8.3.3 MKW0xxx SPI Transaction Timing
As defined in Section 8.3.2, the SPI transaction protocol is composed of two or more bytes per frame.
Although the transceiver is capable of a continuous bit transfer for the entire frame, the MCU SPI port only
transfers data in bursts of 8 bits. There are implications in the way the MCU SPI is programmed and used:
• The MCU SS signal -
— Cannot be programmed for SPI module master mode driven operation
— Port signal PTE3 must be enabled and programmed as a GPIO output to provide the required
SS signal timing
• The transaction bytes are sent as a bursts as allowed by the MCU 8-bit SPI module.
Because the MCU is embedded in the SiP and the transceiver only supports the one clock format, the MCU
SPI must be programmed for this clock mode, i.e., clock phase control bit CPHA = 0 and the clock polarity
control bit CPOL = 0. In addition, the MSB-first option must be selected.
Figure 8-3 illustrates a simple single read access transaction timing. The top part of the figure shows the
SPI timing for a single byte transfer. For the complete frame, the SS signal goes low and stays low for both
byte transfers. The byte transfers are actually accomplished as two operations for the MCI SPI peripheral
block.