NXP Semiconductors MKW01Z128, Reference Manual, Page: 191 / 884

Signal m
ultiple
xing
Module signals
Register
access
16-bit SAR ADC
Peripheral bus
controller 0
Other peripherals
Figure 1-22. 16-bit SAR ADC configuration
Table 1-32. Reference links to related information
Topic Related module Reference
Full description 16-bit SAR ADC 16-bit SAR ADC
System memory map — System memory map
Clocking — Clock distribution
Power management — Power management
Signal multiplexing Port control Signal multiplexing
1.7.1.1 ADC instantiation information
This device contains one 16-bit successive approximation ADC.
The ADC supports both software and hardware triggers. The hardware trigger sources are
listed in the
Module-to-Module section .
The number of ADC channels present on the device is determined by the pinout of the
specific device package and is shown in the following table.
Table 1-33. Number of MKW01xxx ADC channels
Device Number of ADC channels
MKW01xxx 12
1.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC that may have considerable
load on the CPU. The ADC supports DMA request functionality for higher performance
when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA
req) on conversion completion.
Analog
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
60 Freescale Semiconductor, Inc.