NXP Semiconductors MKW01Z128, Reference Manual

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Sub 1 GHz Transceiver Architecture Description
MKW01xxRM Reference Manual, Rev. 3, 04/2016
5-4 Freescale Semiconductor, Inc.
5.5.3 PLL Architecture
The frequency synthesizer generating the LO frequency for both the receiver and the transmitter is a
fractional-N sigma-delta PLL. The PLL incorporates a third order loop capable of fast auto-calibration,
and it has a fast switching-time. The VCO and the loop filter are both fully integrated, removing the need
for an external tight-tolerance, high-Q inductor in the VCO tank circuit.
5.5.3.1 VCO
The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to
reduce any LO leakage in receiver mode, to improve the quadrature precision of the receiver, and to reduce
the pulling effects on the VCO during transmission.
The VCO calibration is fully automated. A coarse adjustment is carried out at power-on reset, and fine
tuning is performed each time the transceiver PLL is activated. Automatic calibration times are fully
transparent to the end-user, as this processing time is included in the
TS_TE and TS_RE specifications.
5.5.3.2 PLL Bandwidth
The bandwidth of the Fractional-N PLL is wide enough to allow for:
• High speed FSK modulation, up to 600 kb/s, inside the PLL bandwidth
• Very fast PLL lock times - enabling both short startup and fast hop times required for frequency
agile applications
5.5.3.3 Carrier Frequency and Resolution
The transceiver PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over
the whole frequency range, and is given by:
The carrier frequency is programmed through RegFrf , split across Addresses 0x07 to 0x09:
NOTE
The Frf setting is split across 3 bytes. A change in the center frequency will
only be taken into account when the least significant byte
FrfLsb in
RegFrfLsb is written. This allows for more complex modulation schemes
such as m-ary FSK, where frequency modulation is achieved by changing
the programmed RF frequency.
5.5.4 Lock Time
PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency,
frequency step, etc. When using the built-in sequencer, the transceiver optimizes the startup time and
F
STEP
F
XOSC
2
19
----------------- =
F
RF
F
STEP
Frf 23 0
( , )

=