NXP Semiconductors MKW01Z128, Reference Manual

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Chapter 17
Peripheral Bridge (AIPS-Lite)
17.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
17.1.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
17.1.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map.
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 291