NXP Semiconductors MKW01Z128, Reference Manual

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Table 2-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
Module
0x4007_1000 113 —
0x4007_2000 114 —
0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC)
0x4007_4000 116 —
0x4007_5000 117 —
0x4007_6000 118 SPI0
0x4007_7000 119 SPI1
0x4007_8000 120 —
0x4007_9000 121 —
0x4007_A000 122 —
0x4007_B000 123 —
0x4007_C000 124 Low-leakage wakeup unit (LLWU)
0x4007_D000 125 Power management controller (PMC)
0x4007_E000 126 System mode controller (SMC)
0x4007_F000 127 Reset control module (RCM)
0x400F_F000 128 GPIO controller
2.6.3 Modules restricted access in user mode
In user mode, for MCG, RCM, SIM (slot 71 and 72), SMC, LLWU, and PMC, reads are
allowed, but writes are blocked and generate bus error.
2.7 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 2-3. PPB memory map
System 32-bit Address Range Resource Additional Range Detail Resource
0xE000_0000–0xE000_DFFF Reserved
0xE000_E000–0xE000_EFFF System Control Space
(SCS) 0xE000_E000–0xE000_E00F Reserved
0xE000_E010–0xE000_E0FF SysTick
0xE000_E100–0xE000_ECFF NVIC
0xE000_ED00–0xE000_ED8F System Control Block
Table continues on the next page...
Private Peripheral Bus (PPB) memory map
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
88 Freescale Semiconductor, Inc.