NXP Semiconductors MKW01Z128, Reference Manual

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The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (TPM counter = CnV) when the TPM counting is down (at the begin of the
pulse width) and when the TPM counting is up (at the end of the pulse width).
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are when the TPM counter is zero.
The other channel modes are not designed to be used with the up-down counter (CPWMS
= 1). Therefore, all TPM channels should be used in CPWM mode when (CPWMS = 1).
pulse width
counter overflow
timer module counter =
MOD
period
(2 x CnV)
(2 x MOD)
timer module counter = 0
channel (n) match
(timer module counting
is down)
channel (n) match
(timer module counting
is up)
counter overflow
timer module counter =
MOD
channel (n) output
Figure 27-12. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the TPM counter reaches the value in the CnV register,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by TPM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (TPM counter = CnV) when counting down, and it is forced low at the channel (n)
match when counting up (see the following figure).
TOF bit
... 7 8 8 7 7 7 6 6 6 5 5 5 4 4 3 3 2 2 1 0 1 ...
previous value
CNT
channel (n) output
counter
overflow
channel (n) match in
down counting
channel (n) match in
up counting
channel (n) match in
down counting
counter
overflow
CHnF bit
MOD = 0x0008
CnV = 0x0005
Figure 27-13. CPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)
match (TPM counter = CnV) when counting down, and it is forced high at the channel (n)
match when counting up (see the following figure).
Functional description
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
536 Freescale Semiconductor, Inc.