NXP Semiconductors MKW01Z128, Reference Manual

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LPTMRx_PSR field descriptions (continued)
Field Description
00 Prescaler/glitch filter clock 0 selected.
01 Prescaler/glitch filter clock 1 selected.
10 Prescaler/glitch filter clock 2 selected.
11 Prescaler/glitch filter clock 3 selected.
29.3.3 Low Power Timer Compare Register (LPTMRx_CMR)
Address: 4004_0000h base + 8h offset = 4004_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
COMPARE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPTMRx_CMR field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
COMPARE Compare Value
When the LPTMR is enabled and the CNR equals the value in the CMR and increments, TCF is set and
the hardware trigger asserts until the next time the CNR increments. If the CMR is 0, the hardware trigger
will remain asserted until the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
when TCF is set.
29.3.4 Low Power Timer Counter Register (LPTMRx_CNR)
NOTE
See LPTMR counter for details on how to read counter value.
Address: 4004_0000h base + Ch offset = 4004_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
COUNTER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPTMRx_CNR field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
558 Freescale Semiconductor, Inc.