NXP Semiconductors MKW01Z128 Page 636 Reference Manual Download

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DAC memory map

Absolute

address

(hex)

Register name

Width

(in bits)

Access Reset value

Section/

page

4003_F000 DAC Data Low Register (DAC0_DAT0L)

R/W

00h

26.4.1/505

4003_F001 DAC Data High Register (DAC0_DAT0H)

R/W

00h

26.4.2/505

4003_F002 DAC Data Low Register (DAC0_DAT1L)

R/W

00h

26.4.1/505

4003_F003 DAC Data High Register (DAC0_DAT1H)

R/W

00h

26.4.2/505

4003_F020 DAC Status Register (DAC0_SR)

R/W

See section

26.4.3/506

4003_F021 DAC Control Register (DAC0_C0)

R/W

00h

26.4.4/507

4003_F022 DAC Control Register 1 (DAC0_C1)

R/W

00h

26.4.5/508

4003_F023 DAC Control Register 2 (DAC0_C2)

R/W

01h

26.4.6/509

26.4.1 DAC Data Low Register (DACx_DATnL)

Address: 4003_F000h base + 0h (2d × i), where i=0d to 1d

Bit

Read

DATA0

Write

Reset

DACx_DATnL field descriptions

Field

Description

DATA0

When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following
formula: V

out

= V

* (1 + DACDAT0[11:0])/4096

When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.

26.4.2 DAC Data High Register (DACx_DATnH)

Address: 4003_F000h base + 1h (2d × i), where i=0d to 1d

Bit

Read

DATA1

Write

Reset

DACx_DATnH field descriptions

Field

Description

7–4

Reserved

This field is reserved.
This read-only field is reserved and always has the value 0.

DATA1

Table continues on the next page...

Chapter 26 12-bit Digital-to-Analog Converter (DAC)

MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016

Freescale Semiconductor, Inc.

505

Summary of Contents for MKW01Z128

Page 1: ...Document Number MKW01xxRM Rev 3 04 2016 MKW01Z128 Sub 1 GHz Low Power Transceiver plus Microcontroller Reference Manual...

Page 2: ...1 7 2 4 Memories and memory interfaces 1 10 1 7 2 5 Clock modules 1 10 1 7 2 6 Security and integrity module 1 10 1 7 2 7 Analog modules 1 11 1 7 2 8 Timer modules 1 11 1 7 2 9 Radio 1 11 1 7 2 10 Co...

Page 3: ...urce 4 11 4 4 3 4 LPO 1 kHz Oscillator 4 11 4 4 4 System Clock Configurations 4 11 4 4 4 1 Single crystal with ClkOut driving MCU EXTAL input 4 12 4 4 4 2 Single Crystal with MCU Using Internal Clock...

Page 4: ...rence 5 12 5 7 3 Continuous Time DAGC 5 12 5 7 4 Quadrature Mixer ADCs Decimators 5 12 5 7 5 Channel Filter 5 13 5 7 6 DC Cancellation 5 14 5 7 7 Complex Filter OOK 5 15 5 7 8 RSSI 5 15 5 7 9 Cordic 5...

Page 5: ...nterface 7 2 7 2 2 FIFO 7 3 7 2 2 1 Overview and Shift Register SR 7 3 7 2 2 2 Size 7 4 7 2 2 3 Interrupt Sources and Flags 7 4 7 2 2 4 FIFO Clearing 7 5 7 2 3 Sync Word Recognition 7 5 7 2 3 1 Overvi...

Page 6: ...n Registers 7 21 7 8 Transmitter Registers 7 25 7 9 Receiver Registers 7 26 7 10 IRQ and Pin Mapping Registers 7 29 7 11 Packet Engine Registers 7 32 7 12 Temperature Sensor Registers 7 36 7 13 Test R...

Page 7: ...MKW01xxRM Reference Manual Rev 3 04 2016 viii Freescale Semiconductor Inc...

Page 8: ...hapter 2 Updated Figure 2 1 MKW01Z128 pinout Updated Table 2 1 Pin Function Description Updated description of pin 58 in Table 2 2 MKW01Z128 Internal Functional Interconnects Chapter 3 Updated Table 3...

Page 9: ...Function Device FFD C Full Function Device Coordinator FLI Frame Length Indicator GTS Guaranteed Time Slot HW Hardware IRQ Interrupt Request ISR Interrupt Service Routine LO Local Oscillator MAC Medi...

Page 10: ...ductor Inc xi SPI Serial Peripheral Interface SSCS Service Specific Convergence Layer SW Software VCO Voltage Controlled Oscillator References The following sources were referenced to produce this boo...

Page 11: ...MKW01xxRM Reference Manual Rev 3 04 2016 xii Freescale Semiconductor Inc...

Page 12: ...safety security peripherals Kinetis MCUs are supported by a market leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners Kinetis W series devices all contain wireless...

Page 13: ...s External watchdog monitor Timing and Control Programmable Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and programmable delay block System Wide operating vo...

Page 14: ...e low power operating modes for optimizing peripheral activity and wakeup times for extended battery life Low leakage wakeup unit and low power timer for time keeping function Industry leading fast wa...

Page 15: ...8 V with fully functional flash and analog peripherals Ambient operating temperature ranges from 40 C to 85 C 1 5 RF transceiver features High Sensitivity down to 120 dBm at 1 2 kbps High Selectivity...

Page 16: ...This codebase provides simple communication and test apps based on drivers PHY utilities available as source code This environment is useful for hardware and RF debug hardware standards certification...

Page 17: ...MKW01Z128 Introduction and Chip Configuration MKW01xxRM Reference Manual Rev 3 04 2016 1 6 Freescale Semiconductor Inc Figure 1 1 MKW01 system level block diagram...

Page 18: ...uirements The transceiver complies with both ETSI and FCC regulatory requirements The major RF communication parameters of the MKW01 transceiver are programmable and most can be dynamically set This f...

Page 19: ...nternal memories include Up to 128KB program flash memory Up to 16KB SRAM Clocks Multiple clock generation options available from internally and externally generated clocks System oscillator from tran...

Page 20: ...modes and signal to clock control logic to resume system clocking After clock restart the NVIC observes the pending interrupt and performs the normal interrupt or event processing Single cycle I O Por...

Page 21: ...flash memory up to 128 KB of the non volatile flash memory that can execute program code Flash memory controller Manages the interface between the device and the on chip flash memory SRAM Up to 16 KB...

Page 22: ...unting be up or updown Six configurable channels for input capture output compare or edge aligned PWM mode Support the generation of an interrupt and or DMA request per channel Support the generation...

Page 23: ...communication to an external device Inter integrated circuit I2C Allows communication between a number of devices Also supports the System Management Bus SMBus Specification version 2 Universal asynch...

Page 24: ...MKW01xxRM Reference Manual Rev 3 04 2016 Freescale Semiconductor Inc 2 1 Chapter 2 MKW01Z128 Pins and Connections 2 1 Device pin assignment Figure 2 1 MKW01Z128 pinout...

Page 25: ...2 ADC0_ SE2 SPI0_MOSI I2C0_SDA SPI0_MISO Digital Input Output MCU Port E Bit 18 ADC0 positive differential analog channel input DP2 ADC0 Single Ended analog channel input 2 SPI module 0 MOSI I2C0 Bus...

Page 26: ...C0 Bus Data TPM module 1 Channel 1 19 VDD Power Input MCU VDD supply input Connect to system VDD supply 20 VSS Power Input MCU Ground Connect to ground 21 PTB2 ADC0_SE12 TSI0_ CH7 I2C0_SCL TPM2_CH0 Di...

Page 27: ..._ TX RTC_CLKOUT CMP0_ OUT I2C1_SDA Digital Input Output MCU Port E Bit 0 SPI module 1 MISO UART module 1 Transmit Real Time Counter Clock Output Comparator 0 Analog voltage Output I2C1 Bus Data 33 PTA...

Page 28: ...connected onboard 50 DIO1 PTE3 SPI1_MISO SPI1_MOSI Digital Input Output Internally connected to Transceiver GPIO bit 1 and MCU Port E bit 3 SPI1 in or out MCU IO and Transceiver IO connected onboard 5...

Page 29: ...SCK PTC5 SPI0_SCK Digital Input Output Internal SPI clock connection between Transceiver SCK and MCU SPI0 port C bit 5 MCU IO and Transceiver IO connected onboard MCU IO must be configured for this co...

Page 30: ...lex control registers The transceiver DIO pins must be programmed to provide desired status 57 MISO PTC7 SPI0_ MISO SPI0_MOSI MISO SPI data from transceiver to MCU 58 NSS PTD0 SPI0_ PCS0 NSS PTD0 prog...

Page 31: ...MKW01Z128 Pins and Connections MKW01xxRM Reference Manual Rev 3 04 2016 2 8 Freescale Semiconductor Inc...

Page 32: ...s the operation of a specific pin 3 2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device For a comprehensive description of the module itself see the...

Page 33: ...iven peripheral function must be assigned to a maximum of one package pin Do not program the same function to more than one pin Table 3 2 Reset State of PORTx_PCRn Register Bit Fields This field of PO...

Page 34: ...appropriate function Likewise where an MCU pin is connected to a transceiver pin off chip Table 3 3 MKW01 Pin Assignments and Signal Multiplexing Sheet 1 of 4 Pin No Pin Name MCU die XCVR die Default...

Page 35: ...PM1_ CH0 18 PTB1 PTB1 ADC0_ SE9 TSI 0_CH6 ADC0_ SE9 TSI0_C H6 PTB1 I2C0_ SDA TPM1_ CH1 19 VDD VDD VDD 20 VSS1 VSS1 VSS1 21 PTB2 PTB2 ADC0_ SE12 TSI0_ CH7 ADC0_ SE12 TSI0_ CH7 PTB2 I2C0_ SCL TPM2_ CH0...

Page 36: ..._TX SPI1_ MOSI 32 PTE0 PTE0 DISABL ED PTE0 SPI1_ MISO UART1 _TX RTC_ CLKO UT CMP0_ OUT I2C1_ SDA 33 PTA20 PTA20 RESET_b PTA20 34 PTE1 PTE1 DISABL ED PTE1 SPI1_ MOSI UART1 _RX SPI1_ MISO I2C1_ SCL 35 V...

Page 37: ...DIO5 DIO51 CLKOU T 55 VDD VDD VDD 56 VDDA VDDA VDDA 57 MISO PTC7 PTC7 MISO CMP0_ IN1 CMP0_ IN1 SPI0_ MISO 58 NSS PTD0 PTD0 NSS DISABL ED PTD0 SPI0_ PCS0 59 SCK PTC5 PTC5 SCK DISABL ED PTC5 LLWU_ P9 SP...

Page 38: ...ally and requires several others to be tied externally This chapter presents information addressing application and operation of the node from a system level The areas considered here are also covered...

Page 39: ...regulated output VR_PA Pin 42 for with RF power boost mode Additional system ground pins include VSS Pin 4 and Pin 20 MCU ground VSSA Pin 3 MCU ATD ground GND Pin 36 transceiver ground GND_PA1 Pin 40...

Page 40: ...be used depending on the application needs Transceiver reset Clock interconnect Additional transceiver status Enhanced packet performance 4 3 1 In package Connections SPI Channel and Status The inter...

Page 41: ...internal pullup device This pin can be disabled or configured as a GPIO PTA20 Asserting RESET low wakes the device from any mode During a pin reset the RCM s SRS0 PIN bit is set The MCU s Low Voltage...

Page 42: ...en high additional current consumption of up to ten milliamps may be seen on VDD 4 3 2 3 MCU Control of Transceiver Reset It is recommended to provide hardware reset capability of the transceiver via...

Page 43: ...Figure 4 4 The device allows for a wide array of system clock configurations Pins are provided for a separate external clock source for the CPU The external clock source can by derived from a crystal...

Page 44: ...s the preferred configuration 4 4 1 Additional Transceiver Status Signals The MKW01Z128 transceiver has a total of six outputs DIO5 DIO0 that can be programmed as status indicators DIO1 and DIO0 are c...

Page 45: ...ance The oscillator needs to see a balanced load capacitance at each terminal and as a result the sum of the stray capacitance of the pcb board device pin XTA or XTB and load capacitor at each termina...

Page 46: ...CU Saves the cost of an additional crystal ClkOut can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset Trimming of the reference oscillator freq...

Page 47: ...U oscillator is a Pierce type that can accommodate crystals or resonators in any of four modes 30 to 40 kHz low frequency range crystal low power 30 to 40 kHz low frequency range crystal high gain 3 3...

Page 48: ...an be enabled to clock the RTC to provide a wake up timer from Stop2 or Stop3 4 4 3 4 LPO 1 kHz Oscillator The LPO is independent of the ICS module and can be used to clock the RTC or COP Its period c...

Page 49: ...forced to a low power condition the MCU can revert to the internal oscillator and FLL 4 4 4 2 Single Crystal with MCU Using Internal Clock Only The single crystal transceiver with the MCU using inter...

Page 50: ...e can be achieved by routing them externally to other GPIO pins PTC4 and PTC3 Freescale software commonly uses DIO4 externally connected to PTD4 DIO5 is also ClkOUT and most commonly externally connec...

Page 51: ...f 160 signals not all are available on the MKW01Z128 There are 8 signals from PTA 5 from PTB 9 from PTC 5 from PTD and 9 from PTE many of which are dedicated to some function This can be seen in Figur...

Page 52: ...PA circuit to be routed through the matching network PA_BOOST optional secondary high power TX PA RFIO RF bidirectional input output used as input only for PA boost mode RXTX digital output to contro...

Page 53: ...er The secondary RF configuration for the transceiver is a dual port mode shown in Figure 4 6 Secondary PA output PA_BOOST is used as the TX port and the standard RFIO pin is used as the RX port Maxim...

Page 54: ...k shown in Figure 4 5 and Figure 4 6 must be evaluated and tuned to its application use and frequency Impedance matching is always required Only a transmission path typically uses any low pass filteri...

Page 55: ...mponent Values vs Frequency Band Component Designation 434 or 490 MHz 868 MHz or 915 MHz Dual Port TX Single Port TX RX Dual Port TX Single Port TX RX L1 22 nH 33 nH 33 nH 33 nH L2 Short Short 2 nH 4...

Page 56: ...performance low cost FSK and OOK RF transceiver for robust frequency agile half duplex bidirectional RF links and where stable and constant RF performance is required over the full operating voltage...

Page 57: ...on This includes the full output power of 17dBm which is maintained from 1 8 to 3 6 V The transceiver voltage source is supplied via pins VBAT1 and VBAT2 See Section 4 2 Power connections for power su...

Page 58: ...hich will only be made available on the output buffer when a stable XO oscillation is achieved An external clock can be used to replace the crystal oscillator for instance a tight tolerance TCXO To do...

Page 59: ...nt to the end user as this processing time is included in the TS_TE and TS_RE specifications 5 5 3 2 PLL Bandwidth The bandwidth of the Fractional N PLL is wide enough to allow for High speed FSK modu...

Page 60: ...e of specifications give an order of magnitude for the expected lock times 5 5 5 Lock Detect Indicator A lock indication signal can be made available on some of the DIO pins and is toggled high when t...

Page 61: ...0 G FSK G MSK OOK Actual BR b s Classical transceiver baud rates multiples of 1 2 kbps 0x68 0x2B 1 2 kbps 1 2 kbps 1199 985 0x34 0x15 2 4 kbps 2 4 kbps 2400 060 0x1A 0x0B 4 8 kbps 4 8 kbps 4799 760 0x...

Page 62: ...ping features are controlled with PaRamp bits in RegPaRamp In FSK mode a Gaussian filter with BT 0 3 0 5 or 1 is used to filter the modulation stream at the input of the sigma delta modulator If the G...

Page 63: ...the Over Current Protection Limit accordingly in RegOcp If PA_BOOST pin is not used the pin can be left floating Table 5 2 Power Amplifier Mode Selection Truth Table Pa0On Pa1On Pa2On Mode Power Range...

Page 64: ...hitecture All the filtering demodulation gain control synchronization and packet handling is performed digitally and this allows a very wide range of bit rates and frequency deviations to be selected...

Page 65: ...transfer mode Packet or Continuous the following series of events takes place when the receiver is enabled The receiver stays in WAIT mode until RssiValue exceeds RssiThreshold for two consecutive sam...

Page 66: ...results if performed while receiving a constant 1 sequence The following figure illustrates the AGC behavior Figure 5 5 AGC Thresholds Settings The following table summarizes the typical performance o...

Page 67: ...In addition to the automatic gain control described in Section 5 7 2 Automatic Gain Control the transceiver is capable of continuously adjusting its gain in the digital domain after the analog to dig...

Page 68: ...l in order to optimize the area and power consumption of the following receiver blocks 5 7 5 Channel Filter The role of the channel filter is to filter out the noise and interferers outside of the cha...

Page 69: ...6 3 3 1 00b 16 6 7 8 3 9 10b 24 5 10 4 5 2 01b 20 5 12 5 6 3 00b 16 5 15 6 7 8 10b 24 4 20 8 10 4 01b 20 4 25 0 12 5 00b 16 4 31 3 15 6 10b 24 3 41 7 20 8 01b 20 3 50 0 25 0 00b 16 3 62 5 31 3 10b 24...

Page 70: ...Local Oscillator is automatically offset by the IF in the OOK receiver A complex filter is implemented on the chip to attenuate the resulting image frequency by typically 30 dB NOTE This filter is aut...

Page 71: ...nly be read when it exceeds RssiThreshold RSSI accuracy depends on all components located between the antenna port and pin RFIO and is therefore limited to a few dB Board level calibration is advised...

Page 72: ...0 5 and below 10 The output of the FSK demodulator can be fed to the Bit Synchronizer described in Section 5 7 12 to provide the companion processor with a synchronous data stream in Continuous mode...

Page 73: ...hes the Floor Threshold programmed in OokFixedThresh The default settings of the OOK demodulator lead to the performance stated in the electrical specification However in applications in which sudden...

Page 74: ...ized as described below for a given number of threshold decrements per bit Refer to RegOokPeak to access those settings 5 7 11 3 Alternative OOK Demodulator Threshold Modes In addition to the Peak OOK...

Page 75: ...zation from the RxReady interrupt The subsequent payload bit stream must have at least one transition form 0 to 1 or 1 to 0 every 16 bits during data transmission The bit rate matching between the tra...

Page 76: ...i in 2 s complement format The time required for an FEI evaluation is 4 times the bit period To ensure a proper behavior of the FEI The operation must be done during the reception of preamble The sum...

Page 77: ...phase to accommodate large LO drifts If the user considers that the received signal may be out of the receiver bandwidth a higher channel filter bandwidth can be programmed in RegAfcBw at the expense...

Page 78: ...i 2 Tafc 2 Tpllafc 5 7 16 Temperature Sensor When temperature is measured the receiver ADC is used to digitize the sensor response Most receiver blocks are disabled and temperature measurement can onl...

Page 79: ...should respect thefollowing equation FDA BRF 2 500kHz where FDA is the Frequency Deviation and BR is the Bit Rate 5 8 1 500 kbps Operation For operation at 500 kbps the following settings are recomme...

Page 80: ...transmit mode Entering transmit mode is also made according to a predefined sequence starting with the wake up of the PA regulator before applying a ramp up on the PA and generating the DCLK clock Th...

Page 81: ...ital delay which depends on the bit rate and the ramp up time In FSK mode this time can be derived from the following equation where PaRamp is the ramp up time programmed in RegPaRamp and Tbit is the...

Page 82: ...oup delay in OOK mode Tcf 34 4 RxBw Analog FE s group delay Channel Filter s group delay DC Cutoff s group delay RSSI sampling XO Started and PLL is locked Tana RSSI sampling Tcf Tdcc Trssi Trssi Rece...

Page 83: ...ight after the RxReady interrupt In Packet mode the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble before the reception of correct Data or Sync Word if e...

Page 84: ...ocedure is illustrated in Figure 6 5 Figure 6 5 Listen Mode Sequence no wanted signal is received NOTE In Idle mode a phase of Listen mode the 32 MHz crystal oscillator of the transceiver is disabled...

Page 85: ...C Timer Accuracy for details 6 3 2 Criteria The criteria taken for detecting a wanted signal and hence deciding to maintain the receiver on is defined by ListenCriteria in RegListen1 6 3 3 End of Cycl...

Page 86: ...tomatically when the calibration is over 6 4 AutoModes Automatic modes of packet handler can be enabled by configuring the related parameters in RegAutoModes The intermediate mode of the chip is calle...

Page 87: ...Handler Some typical examples of AutoModes usage are described below Automatic transmission AutoTx Mode Sleep IntermediateMode TX EnterCondition FifoLevel ExitCondition PacketSent Automatic reception...

Page 88: ...locks which are described in the following paragraphs Figure 7 1 MKW01Z128 Data Processing Conceptual View The MKW01Z128 implements several data operation modes each with their own data path through t...

Page 89: ...te is sent and a read byte is received for the read access The NSS pin goes low at the begin of the frame and goes high after the data byte BURST access the address byte is followed by several data by...

Page 90: ...nly 1 data byte transferred During the write access the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation 7 2 2 FIFO 7 2 2...

Page 91: ...ifoFull interrupt source is high when the last FIFO byte i e the whole FIFO is full Otherwise it is low FifoOverrunFlag FifoOverrunFlag is set when a new byte is written by the user in TX or Standby m...

Page 92: ...tected This is illustrated in Figure 7 5 below Figure 7 5 Sync Word Recognition During the comparison of the demodulated data the first bit received is compared with bit 7 MSB of RegSyncValue1 and the...

Page 93: ...to via SyncTol Value The Sync word value is configured in SyncValue 63 0 In Packet mode this field is also used for Sync word generation in TX mode NOTE SyncValue choices containing 0x00 bytes are no...

Page 94: ...xReady TxReady 10 LowBat LowBat AutoMode Data LowBat LowBat 11 ModeReady PllLock TxReady Data PllLock ModeReady Tx FS Rx Sleep Stdby Mode Diox Mapping DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 00 FifoFull FifoNot...

Page 95: ...from the de modulator is directly accessed by the MCU on the bidirectional DIO2 DATA pin The FIFO and packet handler are thus inactive Figure 7 6 Continuous Mode Conceptual View 7 4 2 TX Processing I...

Page 96: ...to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the MCU bit synchronizer is automatically enabled in Packet mode 7 5 Packet Mode 7 5 1 General Descripti...

Page 97: ...mize RF overhead no length byte field is required All nodes whether TX only RX only or TX RX should be programmed with the same packet length value The length of the payload is limited to 255 bytes if...

Page 98: ...culation In this mode the payload must contain at least 2 bytes i e length address or message byte An illustration of a variable length packet is shown below It contains the following fields Preamble...

Page 99: ...on The CRC detection in RX is also not supported in this mode of the packet handler however CRC generation in TX is operational The interrupts like CrcOk PayloadReady are not available either An unlim...

Page 100: ...ing the result on CrcOk Only the payload including optional address and length fields is made available in the FIFO When the RX mode is enabled the demodulator receives the preamble followed by the de...

Page 101: ...ce the complete packet has been received The data is read from the FIFO decrypted and written back to FIFO The PayloadReady interrupt is issued once the decrypted data is ready in the FIFO for reading...

Page 102: ...p 2 until the entire message has been written to the FIFO PacketSent will fire when the last bit of the packet has been sent For RX FIFO must be unfilled on the fly during RX to prevent FIFO overrun 1...

Page 103: ...cepted and processed otherwise it is discarded This additional check with a constant is useful for implementing broadcast in a multi node networks Please note that the received address byte as part of...

Page 104: ...es a DC bias in the transmitted signal The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth It also introduces data dependencies in the normal operat...

Page 105: ...10 A 9 bit LFSR is used to generate a random sequence The payload and 2 byte CRC checksum is then XORed with this random sequence as shown below The data is de whitened on the receiver side by XORing...

Page 106: ...lection and Output Power control 0x12 RegPaRamp 0x09 Control of the PA ramp time in FSK mode 0x13 RegOcp 0x1A Over Current Protection control 0x14 Reserved14 0x40 0x15 Reserved15 0xB0 0x16 Reserved16...

Page 107: ...ig 0x98 Sync Word Recognition control 0x2F 0x36 RegSyncValue1 8 0x00 0x01 Sync Word bytes 1 through 8 0x37 RegPacketConfig1 0x10 Packet mode settings 0x38 RegPayloadLength 0x40 Payload length setting...

Page 108: ...Mode Default Value Description RegFifo 0x00 7 0 Fifo rw 0x00 FIFO data input output RegOpMode 0x01 7 SequencerOff rw 0 Controls the automatic Sequencer 0 Operating mode as selected with Mode bits in...

Page 109: ...with fcutoff 2 BR 11 reserved RegBitrateMsb 0x03 7 0 BitRate 15 8 rw 0x1a MSB of Bit Rate Chip Rate when Manchester encoding is enabled RegBitrateLsb 0x04 7 0 BitRate 7 0 rw 0x0b LSB of Bit Rate Chip...

Page 110: ...n rw 0 Improved AFC routine for signals with modulation index lower than 2 0 Standard AFC routine 1 Improved AFC routine 4 0 r 00000 unused RegLowBat 0x0C 7 5 r 000 unused 4 LowBatMonitor rw Real time...

Page 111: ...stays in RX mode Listen mode stops and must be disabled 01 chip stays in RX mode until PayloadReady or Timeout interrupt occurs It then goes to the mode defined by Mode Listen mode stops and must be...

Page 112: ...utput power setting with 1 dB steps Pout 18 OutputPower dBm with PA0 or PA1 Pout 2 to 17 dBm with PA1 and PA2 valid range of OutputPower is 10000 through 11111 only Do not set to 0xxxx when using PA2...

Page 113: ...r 001 Current LNA gain set either manually or by the AGC 2 0 LnaGainSelect rw 000 LNA gain setting 000 gain set by the internal AGC loop 001 G1 highest gain 010 G2 highest gain 6 dB 011 G3 highest ga...

Page 114: ...ulator 000 0 5 dB 001 1 0 dB 010 1 5 dB 011 2 0 dB 100 3 0 dB 101 4 0 dB 110 5 0 dB 111 6 0 dB 2 0 OokPeakThreshDec rw 000 Period of decrement of the RSSI threshold in the OOK demodulator 000 once per...

Page 115: ...in RX mode Always reads 0 0 AfcStart w 0 Triggers an AFC when set Always reads 0 RegAfcMsb 0x1F 7 0 AfcValue 15 8 r 0x00 MSB of the AfcValue 2 s complement format RegAfcLsb 0x20 7 0 AfcValue 7 0 r 0x...

Page 116: ...ion RegDioMapping1 0x25 7 6 Dio0Mapping rw 00 Mapping of pins DIO0 to DIO5 See Table 7 2 for mapping in Continuous mode See Table 7 3 for mapping in Packet mode 5 4 Dio1Mapping rw 00 3 2 Dio2Mapping r...

Page 117: ...in FS RX or TX when the PLL is locked Cleared when it is not 3 Rssi rwc 0 Set in RX when the RssiValue exceeds RssiThreshold Cleared when leaving RX 2 Timeout r 0 Set when a timeout occurs see Timeout...

Page 118: ...when the payload is ready i e last byte received and CRC if enabled and CrcAutoClearOff is cleared is Ok Cleared when FIFO is empty 1 CrcOk r 0 Set in RX when the CRC of the payload is Ok Cleared when...

Page 119: ...word SyncSize 1 bytes 2 0 SyncTol rw 000 Number of tolerated bit errors in Sync word RegSyncValue1 0x2f 7 0 SyncValue 63 56 rw 0x01 1st byte of Sync word MSB byte Used if SyncOn is set RegSyncValue2...

Page 120: ...r FIFO and restart new packet reception No PayloadReady interrupt issued 1 Do not clear FIFO PayloadReady interrupt issued 2 1 AddressFiltering rw 00 Defines address based filtering in RX 00 None Off...

Page 121: ...de RX 11 Transmitter mode TX RegFifoThresh 0x3C 7 TxStartCondition rw 1 Defines the condition to start packet transmission 0 FifoLevel i e the number of bytes in the FIFO exceeds FifoThreshold 1 FifoN...

Page 122: ...79 72 w 0x00 7th byte of cipher key RegAesKey8 0x45 7 0 AesKey 71 64 w 0x00 8th byte of cipher key RegAesKey9 0x46 7 0 AesKey 63 56 w 0x00 9th byte of cipher key RegAesKey10 0x47 7 0 AesKey 55 48 w 0...

Page 123: ...e Name Mode Default Value Description RegTestLna 0x58 7 0 SensitivityBoost rw 0x1B High sensitivity or normal sensitivity mode 0x1B Normal mode 0x2D High sensitivity mode RegTestTcxo 0x59 7 0 reserved...

Page 124: ...ure 8 1 shows all the SiP interconnections with the SPI bus highlighted Figure 8 1 MKW01 Internal Interconnects Highlighting SPI Bus Table 2 2 in Chapter 2 provides a complete listing of the MKW01 onb...

Page 125: ...ock Diagram This section shows the system level diagram for the SPI Figure 8 2 shows the SPI modules of the MCU and transceiver in the master slave arrangement Figure 8 2 SPI System Block Diagram The...

Page 126: ...Slave In MOSI The Master Out Slave In MOSI signal presents incoming data from the host to the transceiver slave input 8 3 1 4 Master In Slave Out MISO The Master In Slave Out MISO signal presents inc...

Page 127: ...nsfer NSS must remain asserted for the entire frame 8 3 3 MKW0xxx SPI Transaction Timing As defined in Section 8 3 2 the SPI transaction protocol is composed of two or more bytes per frame Although th...

Page 128: ...he maximum SPI clock baud rate is the peripheral clock The default bus clock rate for some versions of Freescale supplied software is 32 MHz which in turn provides an 8 MHz SPI baud rate Table 8 1 Tra...

Page 129: ...MKW01Z128 Transceiver MCU SPI Interface MKW01xxRM Reference Manual Rev 3 04 2016 8 6 Freescale Semiconductor Inc...

Page 130: ...MKW01xxRM Reference Manual Rev 3 04 2016 Freescale Semiconductor Inc A 1 Appendix A MKW01Z128 MCU Reference Manual...

Page 131: ...MKW01Z128 MCU Reference Manual MKW01xxRM Reference Manual Rev 3 04 2016 A 2 Freescale Semiconductor Inc...

Page 132: ...MKW01Z128 MCU Reference Manual Sub 1 GHz Low Power Transceiver plus Microcontroller Reference Manual Microcontroller Information Document Number MKW01xxRM Rev 3 04 2016...

Page 133: ...MKW01Z128 MCU Reference Manual Rev 3 04 2016 2 Freescale Semiconductor Inc...

Page 134: ...ode controller SMC configuration 40 1 4 3 PMC configuration 40 1 4 4 Low Leakage Wake up Unit LLWU Configuration 41 1 4 5 MCM configuration 43 1 4 6 Crossbar light switch configuration 44 1 4 7 Periph...

Page 135: ...ion 74 1 9 2 I2C configuration 75 1 9 3 UART configuration 76 1 10 Human machine interfaces HMI 77 1 10 1 GPIO configuration 77 1 10 2 TSI configuration 79 Chapter 2 Memory Map 2 1 Introduction 81 2 2...

Page 136: ...ts 95 3 5 1 Clock divider values after reset 96 3 5 2 VLPR mode clocking 96 3 6 Clock gating 97 3 7 Module clocks 97 3 7 1 PMC 1 kHz LPO clock 98 3 7 2 COP clocking 98 3 7 3 RTC clocking 99 3 7 4 LPTM...

Page 137: ...heral Doze 116 5 2 5 Clock gating 117 5 3 Power modes 117 5 4 Entering and exiting power modes 119 5 5 Module operation in low power modes 120 Chapter 6 Debug 6 1 Introduction 125 6 2 Debug port pin d...

Page 138: ..._ISFR 145 7 6 Functional description 145 7 6 1 Pin control 145 7 6 2 Global pin control 146 7 6 3 External interrupts 146 Chapter 8 System Integration Module SIM 8 1 Introduction 149 8 1 1 Features 14...

Page 139: ..._UIDL 171 8 2 17 COP Control Register SIM_COPC 172 8 2 18 Service COP SIM_SRVCOP 173 8 3 Functional description 173 Chapter 9 System Mode Controller SMC 9 1 Introduction 175 9 2 Modes of operation 175...

Page 140: ...PMC_REGSC 200 Chapter 11 Low Leakage Wakeup Unit LLWU 11 1 Reserved Bits in LLWU_PE3 and LLWU_F2 Registers 203 11 2 Introduction 203 11 2 1 Features 203 11 2 2 Modes of operation 204 11 2 3 Block dia...

Page 141: ...2 3 Reset Pin Filter Control register RCM_RPFC 226 12 2 4 Reset Pin Filter Width register RCM_RPFW 227 Chapter 13 Bit Manipulation Engine BME 13 1 Introduction 229 13 1 1 Overview 230 13 1 2 Features...

Page 142: ...ternal signal description 261 15 3 Memory map and register definition 262 15 3 1 MTB_RAM Memory Map 262 15 3 2 MTB_DWT Memory Map 274 15 3 3 System ROM Memory Map 284 Chapter 16 Crossbar Switch Lite A...

Page 143: ...ster DMAMUXx_CHCFGn 307 18 4 Functional description 308 18 4 1 DMA channels with periodic triggering capability 309 18 4 2 DMA channels with no triggering capability 311 18 4 3 Always enabled DMA sour...

Page 144: ...20 3 Memory Map Register Definition 338 20 3 1 MCG Control 1 Register MCG_C1 338 20 3 2 MCG Control 2 Register MCG_C2 340 20 3 3 MCG Control 3 Register MCG_C3 341 20 3 4 MCG Control 4 Register MCG_C4...

Page 145: ...ule initialization sequence 359 20 5 2 Using a 32 768 kHz reference 361 20 5 3 MCG mode switching 362 Chapter 21 Oscillator OSC 21 1 Introduction 371 21 2 Features and Modes 371 21 3 Block Diagram 372...

Page 146: ...ule FTFA 23 1 Introduction 387 23 1 1 Features 388 23 1 2 Block Diagram 388 23 1 3 Glossary 389 23 2 External Signal Description 390 23 3 Memory Map and Registers 390 23 3 1 Flash Configuration Field...

Page 147: ...ower VDDA 430 24 3 2 Analog Ground VSSA 430 24 3 3 Voltage Reference Select 430 24 3 4 Analog Channel Inputs ADx 431 24 3 5 Differential Analog Channel Inputs DADx 431 24 4 Memory map and register def...

Page 148: ...ter ADCx_CLMS 450 24 4 20 ADC Minus Side General Calibration Value Register ADCx_CLM4 451 24 4 21 ADC Minus Side General Calibration Value Register ADCx_CLM3 451 24 4 22 ADC Minus Side General Calibra...

Page 149: ...Register 0 CMPx_CR0 486 25 2 2 CMP Control Register 1 CMPx_CR1 487 25 2 3 CMP Filter Period Register CMPx_FPR 488 25 2 4 CMP Status and Control Register CMPx_SCR 489 25 2 5 DAC Control Register CMPx_D...

Page 150: ...a High Register DACx_DATnH 505 26 4 3 DAC Status Register DACx_SR 506 26 4 4 DAC Control Register DACx_C0 507 26 4 5 DAC Control Register 1 DACx_C1 508 26 4 6 DAC Control Register 2 DACx_C2 509 26 5 F...

Page 151: ...TUS 524 27 3 7 Configuration TPMx_CONF 526 27 4 Functional description 527 27 4 1 Clock domains 528 27 4 2 Prescaler 528 27 4 3 Counter 529 27 4 4 Input Capture Mode 532 27 4 5 Output Compare Mode 532...

Page 152: ...ained timers 550 28 5 Initialization and application information 550 28 6 Example configuration for chained timers 551 28 7 Example configuration for the lifetime timer 552 Chapter 29 Low Power Timer...

Page 153: ...2 1 RTC Time Seconds Register RTC_TSR 565 30 2 2 RTC Time Prescaler Register RTC_TPR 565 30 2 3 RTC Time Alarm Register RTC_TAR 566 30 2 4 RTC Time Compensation Register RTC_TCR 566 30 2 5 RTC Contro...

Page 154: ...Register SPIx_S 583 31 3 2 SPI Baud Rate Register SPIx_BR 587 31 3 3 SPI Control Register 2 SPIx_C2 588 31 3 4 SPI Control Register 1 SPIx_C1 589 31 3 5 SPI Match Register low SPIx_ML 591 31 3 6 SPI m...

Page 155: ...s 619 32 1 2 Modes of operation 620 32 1 3 Block diagram 620 32 2 Register definition 622 32 2 1 UART Baud Rate Register High UARTx_BDH 623 32 2 2 UART Baud Rate Register Low UARTx_BDL 624 32 2 3 UART...

Page 156: ...48 33 2 1 Detailed signal descriptions 648 33 3 Register definition 648 33 3 1 UART Baud Rate Register High UARTx_BDH 649 33 3 2 UART Baud Rate Register Low UARTx_BDL 650 33 3 3 UART Control Register...

Page 157: ...34 2 4 Port Toggle Output Register GPIOx_PTOR 678 34 2 5 Port Data Input Register GPIOx_PDIR 679 34 2 6 Port Data Direction Register GPIOx_PDDR 679 34 3 FGPIO memory map and register definition 680 34...

Page 158: ...onal description 695 35 4 1 Capacitance measurement 696 35 4 2 TSI measurement result 699 35 4 3 Enable TSI module 699 35 4 4 Software and hardware trigger 699 35 4 5 Scan times 699 35 4 6 Clock setti...

Page 159: ...8 I2C Range Address register I2Cx_RA 725 36 3 9 I2C SMBus Control and Status register I2Cx_SMB 725 36 3 10 I2C Address Register 2 I2Cx_A2 727 36 3 11 I2C SCL Low Timeout Register High I2Cx_SLTH 727 3...

Page 160: ...cts 1 2 1 Interconnection overview The following table captures the module to module interconnections for this device Table 1 1 Module to module interconnects Peripheral Signal to Peripheral Use Case...

Page 161: ...CSR TPS CMP0 CMP0_OUT to TPM1 CH0 Input capture SIM_SOPT4 TPM1CH0SRC CMP0 CMP0_OUT to TPM2 CH0 Input capture SIM_SOPT4 TPM2CH0SRC CMP0 CMP0_OUT to UART0_RX IR interface SIM_SOPT5 UART0RXSRC CMP0 CMP0_...

Page 162: ...ption PIT TIF1 to DMA CH1 DMA HW Trigger DMA MUX register option 1 2 2 Analog reference options Several analog blocks have selectable reference voltages as shown in Table 1 2 These options allow analo...

Page 163: ...lock distribution Power management Power management System instruction data bus module Crossbar switch Crossbar switch Debug Serial wire debug SWD Debug Interrupts Nested vectored interrupt controller...

Page 164: ...Multi drop Support SWMD 0 Absent Do not include serial wire support for multi drop System Tick Timer SYST 1 Present Implements system tick timer for CM4 compatibility DAP Target ID TARGETID 0 User Pr...

Page 165: ...s If you see this term it also means this term Privileged Supervisor Unprivileged or user User 1 3 2 Nested vectored interrupt controller NVIC configuration This section summarizes how the module has...

Page 166: ...3 2 2 Non maskable interrupt The non maskable interrupt request to the NVIC is controlled by the external NMI signal The pin the NMI signal is multiplexed on must be configured for the NMI function t...

Page 167: ...0x0000_0044 17 1 0 DMA DMA channel 1 transfer complete and error 0x0000_0048 18 2 0 DMA DMA channel 2 transfer complete and error 0x0000_004C 19 3 0 DMA DMA channel 3 transfer complete and error 0x00...

Page 168: ...4 1 3 2 3 1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the SPI0 interrupt The following table is an excerpt of the SPI0 row fro...

Page 169: ...links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested vectored interrupt controller NVIC...

Page 170: ...bled LPTMR Any interrupt provided clock remains enabled SPI Slave mode interrupt 1 4 System modules 1 4 1 SIM configuration This section summarizes how the module has been configured in the chip For a...

Page 171: ...n Topic Related module Reference Full description System mode controller SMC SMC System memory map System memory map Power management Power management Power management controller PMC PMC Low leakage w...

Page 172: ...System memory map Power management Power management Full description System mode controller SMC System Mode Controller Low leakage wakeup unit LLWU LLWU Reset control module RCM Reset 1 4 4 Low Leaka...

Page 173: ...ller Wake up requests LLWU wake up sources 1 4 4 1 LLWU interrupt NOTE Do not mask the LLWU interrupt when in LLS mode Masking the interrupt prevents the device from exiting stop mode when a wakeup is...

Page 174: ...sive description of the module itself see the module s dedicated chapter Miscellaneous Control Module MCM Transfers ARM Cortex M0 core Flash Memory Controller Transfers Figure 1 8 MCM configuration Ta...

Page 175: ...RAMU Peripherals Figure 1 9 Crossbar light switch integration Table 1 17 Reference links to related information Topic Related module Reference Full description Crossbar switch Crossbar switch System m...

Page 176: ...on This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Peripherals Transfers AIPS Lite periph...

Page 177: ...module itself see the module s dedicated chapter DMA Request Multiplexer DMA controller Requests Module Module Module Peripheral bridge 0 Register access Channel request Figure 1 11 DMA request multi...

Page 178: ...Source description Async DMA capable 0 Channel disabled1 1 Reserved Not used 2 UART0 Receive Yes 3 UART0 Transmit Yes 4 UART1 Receive 5 UART1 Transmit 6 UART2 Receive 7 UART2 Transmit 8 Reserved 9 Res...

Page 179: ...Reserved 48 Reserved 49 Port control module Port A Yes 50 Reserved 51 Port control module Port C Yes 52 Port control module Port D Yes 53 Reserved 54 TPM0 Overflow Yes 55 TPM1 Overflow Yes 56 TPM2 Ove...

Page 180: ...ge 0 Register access Transfers DMA Multiplexer Figure 1 12 DMA Controller configuration Table 1 21 Reference links to related information Topic Related module Reference Full description DMA controller...

Page 181: ...gets lost and fails to reset the COP counter before it times out a system reset is generated to force the system back to a known starting point After any reset the COP watchdog is enabled If the COP...

Page 182: ...elected windowed COP operation is not available The COP counter is initialized by the first writes to SIM_COPC and after any system reset Subsequent writes to SIM_COPC have no effect on COP operation...

Page 183: ...This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Register access Peripheral bridge Multipu...

Page 184: ...ed information Topic Related module Reference Full description OSC OSC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port contro...

Page 185: ...e s dedicated chapter Register access Flash memory Transfers Flash memory controller Peripheral bus controller 0 Figure 1 16 Flash memory configuration Table 1 26 Reference links to related informatio...

Page 186: ...d in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000 See Flash memory sizes for details of supported ranges Access to the flash mem...

Page 187: ...w the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter See MCM_PLACR register description for details on the reset configu...

Page 188: ...ore 1 6 3 1 SRAM sizes This device contains SRAM which could be accessed by bus masters through the cross bar switch The amount of SRAM for the device covered in this document is shown in the followin...

Page 189: ...ustrated in the following figure SRAM_U 0x2000_0000 SRAM size 1 4 SRAM_L 0x1FFF_FFFF SRAM size 3 4 0x2000_0000 SRAM_size 4 0x2000_0000 SRAM_size 3 4 1 Figure 1 20 SRAM blocks memory map For example fo...

Page 190: ...gement 1 6 4 1 System Register file This device includes a 32 byte register file that is powered in all power modes Also it retains contents during low voltage detect LVD events and is only reset duri...

Page 191: ...ADC supports both software and hardware triggers The hardware trigger sources are listed in the Module to Module section The number of ADC channels present on the device is determined by the pinout o...

Page 192: ...SE6a 00111 AD7a Reserved Reserved 00100 AD4b Reserved Reserved 00101 AD5b Reserved Reserved 00110 AD6b Reserved ADC0_SE6b 00111 AD7b Reserved ADC0_SE7b 01000 AD8 Reserved ADC0_SE8 01001 AD9 Reserved A...

Page 193: ...ated VDDA and VSSA pins This device contains separate VREFH and VREFL pins 1 7 1 5 Alternate clock For this device the alternate clock is connected to the external reference clock OSCERCLK NOTE This c...

Page 194: ...gnment table for a summary of CMP input connections for this device The CMP also includes one 6 bit DAC with a 64 tap resistor ladder network which provides a selectable voltage reference for applicat...

Page 195: ...nce at the same time is negatively impacted VDD Vin2 input 1 7 2 4 CMP trigger mode The CMP and 6 bit DAC sub block supports trigger mode operation when CMP_CR1 TRIGM is set When trigger mode is enabl...

Page 196: ...chapter Signal multiplexing Module signals Register access 12 bit DAC Peripheral bus controller 0 Other peripherals Figure 1 24 12 bit DAC configuration Table 1 36 Reference links to related informati...

Page 197: ...ly See Table 1 2 for ADC reference selection 1 7 3 4 12 bit DAC reference DAC reference can be tied to VREFH or VDDA See Table 1 2 NOTE DAC and ADC use the same reference simultaneously some degradati...

Page 198: ...only as basic TPM function do not support quadrature decoder function and all can be functional in Stop VLPS mode The clock source is either external or internal in Stop VLPS mode The following table...

Page 199: ...valid operation the selected external clock must be less than half the frequency of the selected TPM clock source 1 8 1 3 Trigger options Each TPM has a selectable trigger input source controlled by T...

Page 200: ...arizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Register access Peripheral bridge Periodic interrupt timer...

Page 201: ...ggers are selected as TPMx trigger sources using the TPMx_CONF TRGSEL bits in the TPM module For more details refer to TPM chapter 1 8 2 4 PIT DAC triggers PIT Channel 0 is configured as the DAC hardw...

Page 202: ...or glitch filter pulse accumulator mode The LPTMR can be clocked from the internal reference clock the internal 1 kHz LPO OSCERCLK or an external 32 768 kHz crystal In VLLS0 mode the clocking option...

Page 203: ...odes LPTMR0_PSR PCS Prescaler glitch filter clock number Chip clock 00 0 MCGIRCLK internal reference clock not available in LLS and VLLS modes 01 1 LPO 1 kHz clock not available in VLLS0 mode 10 2 ERC...

Page 204: ...f the System OSC configuring the OSC for 32 kHz crystal operation in all power modes except VLLS0 and through any System Reset When OSCE is enabled the RTC also overrides the capacitor configurations...

Page 205: ...emory map Clocking Clock distribution Signal multiplexing Port control Signal multiplexing 1 9 1 1 SPI instantiation information This device contains two SPI module that supports 16 bit data length SP...

Page 206: ...clock and IIC1 is clocked by the system clock Clocking IIC1 at the faster system clock is needed to support standard IIC communication rates of 100 kbit s in VLPR mode When the package pins associated...

Page 207: ...ck distribution Power management Power management Signal multiplexing Port control Signal multiplexing 1 9 3 1 UART0 overview The UART0 module supports basic UART with DMA interface function x4 to x32...

Page 208: ...s to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock distribution Power management Power management Crossbar switch Cro...

Page 209: ...ew rate enable control Yes Yes Yes Yes Yes Slew rate enable at reset PTA3 PTA14 PTA15 PTA16 PTA17 Disabled Others Enabled PTB10 PTB11 PTB16 PTB17 Disabled Others Enabled PTC3 PTC4 PTC5 PTC6 PTC7 Disab...

Page 210: ...space can be accomplished referencing the aliased slot 15 at address 0x4000_F000 Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000 1 10 2 TSI configuration T...

Page 211: ...TSI channels present on the device is determined by the pinout of the specific device package and is shown in the following table Table 1 50 Number of MKW01xxx TSI channels Device TSI channels MKW01xx...

Page 212: ..._0000 0x1FFF_DFFF Reserved 0x1FFF_E000 0x1FFF_FFFF SRAM_L Lower SRAM All masters 0x2000_0000 0x2000_5FFF2 SRAM_U Upper SRAM All masters 0x2000_6000 0x3FFF_FFFF Reserved 0x4000_0000 0x4007_FFFF AIPS Pe...

Page 213: ...ee SRAM ranges for details 3 Includes BME operations to GPIO at slot 15 based at 0x4000_F000 2 3 Flash memory map The flash memory and the flash registers are located at different base addresses as sh...

Page 214: ...the memory map See SRAM ranges for details Access to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the ap...

Page 215: ...via their clock gate control bits in the SIM registers disable the associated AIPS slots Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error te...

Page 216: ...0x4000_D000 13 0x4000_E000 14 0x4000_F000 15 GPIO controller aliased to 0x400F_F000 0x4001_0000 16 0x4001_1000 17 0x4001_2000 18 0x4001_3000 19 0x4001_4000 20 0x4001_5000 21 0x4001_6000 22 0x4001_700...

Page 217: ...56 Timer PWM TPM 0 0x4003_9000 57 Timer PWM TPM 1 0x4003_A000 58 Timer PWM TPM 2 0x4003_B000 59 Analog to digital converter 0 ADC0 0x4003_C000 60 0x4003_D000 61 Real time clock RTC 0x4003_E000 62 0x40...

Page 218: ...005_7000 87 0x4005_8000 88 0x4005_9000 89 0x4005_A000 90 0x4005_B000 91 0x4005_C000 92 0x4005_D000 93 0x4005_E000 94 0x4005_F000 95 0x4006_0000 96 0x4006_1000 97 0x4006_2000 98 0x4006_3000 99 0x4006_4...

Page 219: ...r MCG RCM SIM slot 71 and 72 SMC LLWU and PMC reads are allowed but writes are blocked and generate bus error 2 7 Private Peripheral Bus PPB memory map The PPB is part of the defined ARM bus architect...

Page 220: ...e Detail Resource 0xE000_ED90 0xE000_EDEF Reserved 0xE000_EDF0 0xE000_EEFF Debug 0xE000_EF00 0xE000_EFFF Reserved 0xE000_F000 0xE00F_EFFF Reserved 0xE00F_F000 0xE00F_FFFF Core ROM Space CRS Chapter 2...

Page 221: ...Private Peripheral Bus PPB memory map MKW01Z128 MCU Reference Manual Rev 3 04 2016 90 Freescale Semiconductor Inc...

Page 222: ...ontroller have selectable clock input See AN4503 Power Management for Kinetis and ColdFire MCUs for further details on the system clocks and their use 3 2 Programming model The selection and multiplex...

Page 223: ...32K OSC32KCLK XTAL_CLK OSCERCLK OSC logic Clock options for some peripherals see note Clock options for some peripherals see note MCGFLLCLK MCGPLLCLK Note See subsequent sections for details on where...

Page 224: ...put of the PLL MCGFLLCLK or MCGPLLCLK may clock some modules In addition this clock is used for UART0 and TPM modules OSCCLK System oscillator output of the internal oscillator or sourced directly fro...

Page 225: ...OP2 mode and Compute Operation SWD Clock Up to 24 MHz Up to 1 MHz SWD_CLK pin In all stop modes Flash clock Up to 24 MHz Up to 1 MHz in BLPE Up to 800 kHz in BLPI MCGOUTCLK clock divider In all stop m...

Page 226: ...eds to be limited to 800 kHz if executing from flash 3 5 Internal clocking requirements The clock dividers are programmed via the CLKDIV registers of the SIM module The following requirements must be...

Page 227: ...riate bits in FTFA_FOPT During the reset sequence if either of the control bits is cleared the system is in a slower clock configuration Upon any system reset the clock dividers return to this configu...

Page 228: ...ule Table 3 2 Module clocks Module Bus interface clock Internal clocks I O interface clocks Core modules ARM Cortex M0 core Platform clock Core clock NVIC Platform clock DAP Platform clock SWD_CLK Sys...

Page 229: ...us clock I2C0_SCL I2C1 System clock I2C1_SCL UART0 Bus clock UART0 clock UART1 UART2 Bus clock Human machine interfaces GPIO Platform clock TSI Bus clock 3 7 1 PMC 1 kHz LPO clock The Power Management...

Page 230: ...power modes SIM_SOPT1 OSC32KSEL OSC32KCLK RTC_CLKIN LPO ERCLK32K to RTC Figure 3 3 RTC clock generation 3 7 4 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be cloc...

Page 231: ...to continue operating in all required low power modes SIM_SOPT2 TPMSRC TPM clock MCGIRCLK OSCERCLK MCGPLLCLK 2 SIM_SOPT2 PLLFLLSEL MCGFLLCLK Figure 3 5 TPM clock generation 3 7 6 SPI clocking SPI0 is...

Page 232: ...has a selectable clock as shown in the following figure UART1 and UART2 modules operate from the bus clock NOTE The chosen clock must remain enabled if the UART0 is to continue operating in all requi...

Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...

Page 234: ...UP MDM DAP system reset Debug reset Debug reset Each of the system reset sources has an associated bit in the System Reset Status SRS registers See the Reset Control Module for register details The MC...

Page 235: ...Reads the start program counter PC from vector table offset 4 Link register LR is set to 0xFFFF_FFFF The on chip peripheral modules are disabled and the non analog I O pins are initially configured as...

Page 236: ...contents and control MCU system states during supply voltage variations The system consists of a power on reset POR circuit and an LVD circuit with a user selectable trip voltage The LVD system is al...

Page 237: ...The MCG module supports an external reference clock If MCG_C6 CME is set the clock monitor is enabled If the external reference falls below floc_low or floc_high as controlled by MCG_C2 RANGE the MCU...

Page 238: ...debug module A software reset causes RCM_SRS1 SW to set 4 2 2 9 Lockup reset LOCKUP The LOCKUP gives immediate indication of seriously errant kernel software This is the result of the core being locke...

Page 239: ...Pin Filter registers and parts of the SIM and MCG The Chip POR also causes the Chip Reset including Early Chip Reset to occur 4 2 3 4 Chip Reset not VLLS The Chip Reset not VLLS reset asserts on all...

Page 240: ...G option bit to 0 See Table 4 2 When this option is selected there could be a short period of contention during a POR ramp where the device drives the pinout low prior to establishing the setting of t...

Page 241: ...ion FOPT register in the Flash Memory module FTFA_FOPT allows the user to customize the operation of the MCU at boot time The register contains read only bits that are loaded from the NVM s option byt...

Page 242: ...ow power mode wake up NOTE When the reset pin has been disabled and security has been enabled by means of the FSEC register a mass erase can be performed only by setting both the Mass Erase and System...

Page 243: ...speed If FTFA_FOPT FAST_INIT is programmed clear the flash initialization switches to slower clock resulting longer recovery times 5 When flash Initialization completes the RESET pin is released If R...

Page 244: ...Partial Stop can be entered from either Run mode or VLP Run mode When configured for PSTOP2 only the core and system clocks are gated and the bus clock remains active The bus masters and bus slaves cl...

Page 245: ...ernal power switches enabling the clock generators in the MCG enabling the system and bus clocks but not the core clock and negating the stop mode signal to the bus masters and bus slaves The only dif...

Page 246: ...asynchronous DMA request 5 2 3 Compute Operation Compute Operation is an execution or compute only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port but pl...

Page 247: ...MCM_CPO CPOACK indicates when entry has completed When exiting Compute Operation in Run mode MCM_CPO CPOACK negates immediately When exiting Compute Operation in VLP Run mode the exit is delayed to a...

Page 248: ...disables the clock to the corresponding module Prior to initializing a module set the corresponding bit in the SCGCx register to enable the clock Before turning off the clock make sure to disable the...

Page 249: ...4 MHz source for the core with the nominal bus and flash clock required to be 800 kHz Alternatively BLPE clock mode can be used with an external clock or the crystal oscillator providing the clock sou...

Page 250: ...M_L are powered off The 32 byte system register file remains powered for customer critical data LPO disabled optional POR brown out detection Sleep Deep Wake up Reset2 1 Resumes Normal Run mode operat...

Page 251: ...ed memories are retained powered Memory is powered to retain contents low power Memory is powered to retain contents in a lower power state OFF Modules are powered off module is in reset state upon wa...

Page 252: ...TOP2 from RUN 1 MHz max in PSTOP2 from VLPR OFF OFF OFF Memory and memory interfaces Flash 1 MHz max access no program No register access in CPO low power low power low power OFF OFF SRAM_U and SRAM_L...

Page 253: ...peration static OFF PIT FF static in CPO FF static static static OFF LPTMR FF FF Async operation FF in PSTOP2 Async operation Async operation Async operation4 RTC FF Async operation in CPO FF Async op...

Page 254: ...LPO clock source is disabled filters will be bypassed during VLLS0 3 STOPCTRL PORPO in the SMC module controls this option 4 LPO clock source is not available in VLLS0 Also to use system OSC in VLLS0...

Page 255: ...Module operation in low power modes MKW01Z128 MCU Reference Manual Rev 3 04 2016 124 Freescale Semiconductor Inc...

Page 256: ...is supported Serial Wire Debug SWD 6 2 Debug port pin descriptions The debug port pins default after POR to their SWD functionality Table 6 1 Serial wire debug pin description Pin name Type Descripti...

Page 257: ...switch thus remaining less intrusive during a debug session It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessib...

Page 258: ...RL STAT AP Select SELECT Read Buffer RDBUFF DP Registers 0x00 0x04 0x08 0x0C Data 31 0 A 3 2 RnW DPACC Data 31 0 A 3 2 RnW APACC Debug Port DP Generic See the ARM Debug Interface v5p1 Supplement Figur...

Page 259: ...debugger time to re initialize debug IP before the debug session continues The Mode Controller captures this bit logic on entry to VLLSx modes Upon exit from VLLSx modes the Mode Controller will hold...

Page 260: ...se is disabled 1 Mass erase is enabled 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled 0 Disabled 1 Enabled 7 LP Enabled Decode of SMC_PMCTRL STOPM field to indic...

Page 261: ...the LLS VLLSx Status Acknowledge bit in MDM AP Control register 11 15 Reserved for future use Always read 0 16 Core Halted Indicates the core has entered Debug Halt mode 17 Core SLEEPDEEP Indicates th...

Page 262: ...The MTB includes trace control registers for configuring and triggering the MTB functions The MTB also supports triggering via TSTART and TSTOP control functions in the MTB DWT module 6 6 Debug in low...

Page 263: ...to the debugger to sync up with the HW the MDM AP Control register can be configured to hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior t...

Page 264: ...in muxing state There is one instance of the PORT module for each port Not all pins within each port are implemented on a specific device 7 2 1 Features The PORT module has the following features Pin...

Page 265: ...d configuration fields are functional in all digital pin muxing modes 7 2 2 Modes of operation 7 2 2 1 Run mode In Run mode the PORT operates normally 7 2 2 2 Wait mode In Wait mode PORT continues to...

Page 266: ...asynchronously to the system clock Negation may occur at any time and can assert asynchronously to the system clock 7 5 Memory map and register definition Any read or write access to the PORT memory...

Page 267: ...section 7 5 1 141 4004_9050 Pin Control Register n PORTA_PCR20 32 R W See section 7 5 1 141 4004_9054 Pin Control Register n PORTA_PCR21 32 R W See section 7 5 1 141 4004_9058 Pin Control Register n P...

Page 268: ...ion 7 5 1 141 4004_A050 Pin Control Register n PORTB_PCR20 32 R W See section 7 5 1 141 4004_A054 Pin Control Register n PORTB_PCR21 32 R W See section 7 5 1 141 4004_A058 Pin Control Register n PORTB...

Page 269: ...section 7 5 1 141 4004_B050 Pin Control Register n PORTC_PCR20 32 R W See section 7 5 1 141 4004_B054 Pin Control Register n PORTC_PCR21 32 R W See section 7 5 1 141 4004_B058 Pin Control Register n P...

Page 270: ...ion 7 5 1 141 4004_C050 Pin Control Register n PORTD_PCR20 32 R W See section 7 5 1 141 4004_C054 Pin Control Register n PORTD_PCR21 32 R W See section 7 5 1 141 4004_C058 Pin Control Register n PORTD...

Page 271: ..._D048 Pin Control Register n PORTE_PCR18 32 R W See section 7 5 1 141 4004_D04C Pin Control Register n PORTE_PCR19 32 R W See section 7 5 1 141 4004_D050 Pin Control Register n PORTE_PCR20 32 R W See...

Page 272: ...E field Varies by port See the Signal Multiplexing and Signal Descriptions chapter for reset values per port PFE field Varies by port See Signal Multiplexing and Signal Descriptions chapter for reset...

Page 273: ...1 ISF flag and DMA request on either edge 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 ISF flag and Interrupt when logic 0 1001 ISF flag and Interrupt on rising edge 1010 ISF flag and...

Page 274: ...r pins that do not support a configurable slew rate Slew rate configuration is valid in all digital pin muxing modes 0 Fast slew rate is configured on the corresponding pin if the pin is configured as...

Page 275: ...isters bits 15 0 that are selected by GPWE 7 5 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25...

Page 276: ...he corresponding flag will be cleared automatically at the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a...

Page 277: ...is not connected or an output pin that has tri stated output buffer is disabled Enabling the internal pull resistor or implementing an external pull resistor will ensure a pin does not float when its...

Page 278: ...t that asserts when the interrupt status flag is set for any enabled interrupt for that port The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writ...

Page 279: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 148 Freescale Semiconductor Inc...

Page 280: ...ck gating control ERCLK32K clock selection UART and TPM clock selection Flash and System RAM size configuration TPM external clock and input capture selection UART receive transmit source selection co...

Page 281: ...F000_0030h 8 2 7 160 4004_8038 System Clock Gating Control Register 5 SIM_SCGC5 32 R W 0000_0182h 8 2 8 162 4004_803C System Clock Gating Control Register 6 SIM_SCGC6 32 R W 0000_0001h 8 2 9 164 4004_...

Page 282: ...his field is reserved This read only field is reserved and always has the value 0 19 18 OSC32KSEL 32K Oscillator Clock Select Selects the 32 kHz clock source ERCLK32K for RTC and LPTMR This field is r...

Page 283: ...PT2 field descriptions Field Description 31 30 Reserved This field is reserved This read only field is reserved and always has the value 0 29 28 Reserved This field is reserved This read only field is...

Page 284: ...by 2 15 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 5 CLKOUTSEL CLKOUT select Selects the clock to output on the CLKOUT pin 000 Reserved 001 Reserve...

Page 285: ...ternal clock driven by TPM_CLKIN0 pin 1 TPM2 external clock driven by TPM_CLKIN1 pin 25 TPM1CLKSEL TPM1 External Clock Pin Select Selects the external pin used to drive the clock to the TPM1 module NO...

Page 286: ...E When TPM1 is not in input capture mode clear this field 00 TPM1_CH0 signal 01 CMP0 output 10 Reserved 11 Reserved Reserved This field is reserved This read only field is reserved and always has the...

Page 287: ...ta Source Select Selects the source for the UART1 receive data 0 UART1_RX pin 1 CMP0 output 5 4 UART1TXSRC UART1 Transmit Data Source Select Selects the source for the UART1 transmit data 00 UART1_TX...

Page 288: ...SB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register 1 ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits ADC0PRETRGSEL...

Page 289: ...1101 RTC seconds 1110 LPTMR0 trigger 1111 Reserved 8 2 6 System Device Identification Register SIM_SDID Address 4004_7000h base 1024h offset 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 290: ...tem SRAM Size Specifies the size of the System SRAM 0000 0 5 KB 0001 1 KB 0010 2 KB 0011 4 KB 0100 8 KB 0101 16 KB 0110 32 KB 0111 64 KB 15 12 REVID Device Revision Number Specifies the silicon implem...

Page 291: ...3 2 1 0 R 0 0 UART2 UART1 UART0 0 0 I2C1 I2C0 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 SIM_SCGC4 field descriptions Field Description 31 28 Reserved This field is reserved This read only field is r...

Page 292: ...s has the value 0 12 UART2 UART2 Clock Gate Control Controls the clock gate to the UART2 module 0 Clock disabled 1 Clock enabled 11 UART1 UART1 Clock Gate Control Controls the clock gate to the UART1...

Page 293: ...ld descriptions Field Description 31 Reserved This field is reserved This read only field is reserved and always has the value 0 30 22 Reserved This field is reserved This read only field is reserved...

Page 294: ...abled 8 7 Reserved This field is reserved This read only field is reserved and always has the value 1 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 TS...

Page 295: ...d 30 Reserved This field is reserved This read only field is reserved and always has the value 0 29 RTC RTC Access Control Controls software access and interrupts to the RTC module 0 Access and interr...

Page 296: ...has the value 0 17 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 Reserved This field is reserved This read only field is reserved and always has the...

Page 297: ...erved This read only field is reserved and always has the value 0 8 2 11 System Clock Divider Register 1 SIM_CLKDIV1 NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode NOTE...

Page 298: ...de by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 27 19 Reserved This field is reserved This read only field is reserved and always has the value 0 18...

Page 299: ...Size Specifies the amount of program flash memory available on the device Undefined values are reserved 0000 8 KB of program flash memory 1 KB protection region 0001 16 KB of program flash memory 1 K...

Page 300: ...S Flash Disable Flash accesses are disabled and generate a bus error and the flash memory is placed in a low power state This field should not be changed during VLP modes Relocate the interrupt vector...

Page 301: ...block flash block 1 For example if MAXADDR0 MAXADDR1 0x10 the first invalid address of flash block 1 is 0x2_0000 0x2_0000 This would be the MAXADDR1 value for a device with 256 KB program flash memor...

Page 302: ...ication Unique identification for the device 8 2 16 Unique Identification Register Low SIM_UIDL Address 4004_7000h base 1060h offset 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 303: ...s the timeout period of the COP COPT along with the COPCLKS field define the COP timeout period 00 COP disabled 01 COP timeout after 25 LPO cycles or 213 bus clock cycles 10 COP timeout after 28 LPO c...

Page 304: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SRVCOP field descriptions Field Description 31 8 Reserved This field is reserved SRVCOP Service COP Register Write 0x55 and then 0...

Page 305: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 174 Freescale Semiconductor Inc...

Page 306: ...ty of that mode This chapter describes all the available low power modes the sequence followed to enter exit each mode and the functionality available while in each of the modes The SMC is able to fun...

Page 307: ...ull power down of certain logic and or memory I O states are held in all modes of operation Several registers are used to configure the various modes of operation for the device The following table de...

Page 308: ...other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid The MCU is placed in a low leakage mode by powering down the internal logic and all...

Page 309: ...tempt to enter VLPR mode using PMCTRL RUNM is blocked and PMCTRL RUNM remains 00b indicating the MCU is still in Normal Run mode NOTE This register is reset on Chip Reset not VLLS and by reset types t...

Page 310: ...very low leakage stop mode VLLSx 0 Any VLLSx mode is not allowed 1 Any VLLSx mode is allowed 0 Reserved This field is reserved This read only field is reserved and always has the value 0 9 3 2 Power...

Page 311: ...0 The previous stop mode entry was successful 1 The previous stop mode entry was aborted STOPM Stop Mode Control When written controls entry into the selected stop mode when Sleep Now or Sleep On Exit...

Page 312: ...als running on bus clock to remain fully functional In PSTOP1 both system and bus clocks are gated 00 STOP Normal Stop mode 01 PSTOP1 Partial Stop with both system and bus clocks disabled 10 PSTOP2 Pa...

Page 313: ...tatus NOTE When debug is enabled the PMSTAT will not update to STOP or VLPS NOTE When a PSTOP mode is enabled the PMSTAT will not update to STOP or VLPS 0000_0001 Current power mode is RUN 0000_0010 C...

Page 314: ...2 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register in ARM core See no...

Page 315: ...olled in System Control Register in ARM core See note 1 VLPS VLPR Interrupt NOTE If VLPS was entered directly from RUN transition 7 hardware forces exit back to RUN and does not allow a transition to...

Page 316: ...and STOPCTRL PSTOPO 01 or 10 then only a Partial Stop mode is entered instead of STOP 3 If PMCTRL STOPM 000 and STOPCTRL PSTOPO 00 then VLPS mode is entered instead of STOP If PMCTRL STOPM 000 and ST...

Page 317: ...e WFI instruction After the instruction is executed the following sequence occurs 1 The CPU clock is gated off immediately 2 Requests are made to all non CPU bus masters to enter Stop mode 3 After all...

Page 318: ...stop mode regulation After this point the interrupt is ignored until the PMC has completed its transition to stop mode regulation When an aborted stop mode entry sequence occurs SMC_PMCTRL STOPA is se...

Page 319: ...their corresponding clock gating control bits in the SIM s registers Before entering this mode the following conditions must be met The MCG must be configured in a mode which is supported during VLPR...

Page 320: ...to be clocked provided they are enabled Clock gating to the peripheral is enabled via the SIM module When an interrupt request occurs the CPU exits WAIT mode and resumes processing in RUN mode beginni...

Page 321: ...and state retention versus functional needs and recovery time may be traded off NOTE All clock monitors must be disabled before entering these low power modes Stop VLPS VLPR VLPW LLSand VLLSx The var...

Page 322: ...d directly from RUN mode exit to VLPR is disabled by hardware and the system will always exit back to RUN In VLPS the on chip voltage regulator remains in its stop regulation state as in VLPR A module...

Page 323: ...w or Sleep On Exit mode the SLEEPDEEP bit is set in the System Control Register in the ARM core and The device is configured as shown in Table 9 2 In VLLS the on chip voltage regulator is in its stop...

Page 324: ...le while the MCU is in LLS or VLLS modes LLS is a state retention mode and all debug operation can continue after waking from LLS even in cases where system wakeup is due to a system reset event Enter...

Page 325: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 194 Freescale Semiconductor Inc...

Page 326: ...tage regulator Active POR providing brown out detect Low voltage detect supporting two low voltage trip points with four warning levels per trip point 10 3 Low voltage detect LVD system This device in...

Page 327: ...voltage condition The low voltage detection threshold is determined by LVDSC1 LVDV After an LVD reset occurs the LVD system holds the MCU in reset until the supply voltage rises above this threshold...

Page 328: ...in the I O are released and default to their reset state In this case no write to REGSC ACKISO is needed 10 5 Memory map and register descriptions Details about the PMC registers can be found here NOT...

Page 329: ...systems that must have LVD always on configure the Power Mode Protection PMPROT register of the SMC module SMC_PMPROT to disallow any very low power or low leakage modes from being enabled See the dev...

Page 330: ...alue 0 LVDV Low Voltage Detect Voltage Select Selects the LVD trip point voltage V LVD 00 Low trip point selected V LVD V LVDL 01 High trip point selected V LVD V LVDH 10 Reserved 11 Reserved 10 5 2 L...

Page 331: ...le Enables hardware interrupt requests for LVWF 0 Hardware interrupt disabled use polling 1 Request a hardware interrupt when LVWF 1 4 2 Reserved This field is reserved This read only field is reserve...

Page 332: ...require the bandgap voltage reference in low power modes of operation set BGEN to continue to enable the bandgap operation NOTE When the bandgap voltage reference is not needed in low power modes clea...

Page 333: ...is in run regulation 1 Reserved This field is reserved NOTE This reserved bit must remain cleared set to 0 0 BGBE Bandgap Buffer Enable Enables the bandgap buffer 0 Bandgap buffer not enabled 1 Bandga...

Page 334: ...low leakage power modes The input sources are described in the device s chip configuration details Each of the available wake up sources can be individually enabled The RESET pin is an additional sour...

Page 335: ...LLS the LLWU is immediately disabled After recovery from VLLS the LLWU continues to detect wake up events until the user has acknowledged the wake up via a write to PMC_REGSC ACKISO 11 2 2 1 LLS mode...

Page 336: ...4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode no debug logic works in the fully functional low leakage mode Upon an exit from the LLS or VLLSx mode the LLWU becomes i...

Page 337: ...LT1 FILTE Pin filter 1 Synchronizer Synchronizer Edge detect LLWU_P15 wakeup occurred Edge detect Pin filter 2 wakeup occurred 2 LLWU_P0 wakeup occurred FILT2 FILTSEL FILT1 FILTSEL FILT2 FILTE Figure...

Page 338: ...t VLLS For more information about the types of reset on this chip refer to the Introduction details LLWU memory map Absolute address hex Register name Width in bits Access Reset value Section page 400...

Page 339: ...nal input pin enabled with any change detection 5 4 WUPE2 Wakeup Pin Enable For LLWU_P2 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 E...

Page 340: ...LWU_P7 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enable...

Page 341: ...s unaffected by reset types that do not trigger Chip Reset not VLLS See the Introduction details for more information Address 4007_C000h base 2h offset 4007_C002h Bit 7 6 5 4 3 2 1 0 Read WUPE11 WUPE1...

Page 342: ...put pin enabled with any change detection 11 4 4 LLWU Pin Enable 4 register LLWU_PE4 LLWU_PE4 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P15 L...

Page 343: ...abled with any change detection WUPE12 Wakeup Pin Enable For LLWU_P12 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin...

Page 344: ...d as wakeup source 1 Internal module flag used as wakeup source 3 WUME3 Wakeup Module Enable For Module 3 Enables an internal module as a wakeup source input 0 Internal module flag not used as wakeup...

Page 345: ...F3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field Description 7 WUF7 Wakeup Flag For LLWU_P7 Indicates that an enabled external wakeup pin...

Page 346: ...that an enabled external wakeup pin was a source of exiting a low leakage power mode To clear the flag write a 1 to WUF1 0 LLWU_P1 input was not a wakeup source 1 LLWU_P1 input was a wakeup source 0 W...

Page 347: ...To clear the flag write a 1 to WUF14 0 LLWU_P14 input was not a wakeup source 1 LLWU_P14 input was a wakeup source 5 WUF13 Wakeup Flag For LLWU_P13 Indicates that an enabled external wakeup pin was a...

Page 348: ...ns the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode For LLS this is the source causing the CPU interrupt flow For VLLS this is the source causing the MC...

Page 349: ...low leakage power mode To clear the flag follow the internal peripheral flag clearing mechanism 0 Module 4 input was not a wakeup source 1 Module 4 input was a wakeup source 3 MWUF3 Wakeup flag For m...

Page 350: ...C000h base 8h offset 4007_C008h Bit 7 6 5 4 3 2 1 0 Read FILTF FILTE 0 FILTSEL Write w1c Reset 0 0 0 0 0 0 0 0 LLWU_FILT1 field descriptions Field Description 7 FILTF Filter Detect Flag Indicates that...

Page 351: ...ead FILTF FILTE 0 FILTSEL Write w1c Reset 0 0 0 0 0 0 0 0 LLWU_FILT2 field descriptions Field Description 7 FILTF Filter Detect Flag Indicates that the filtered external wakeup pin selected by FILTSEL...

Page 352: ...pin The LLWU implements optional 3 cycle glitch filters based on the LPO clock A detected external pin is required to remain asserted until the enabled glitch filter times out Additional latency of u...

Page 353: ...ware before entering LLS or VLLSx mode to avoid an immediate exit from the mode Flags associated with external input pins filtered and unfiltered must also be cleared by software prior to entry to LLS...

Page 354: ...registers provide reset status information and reset filter control NOTE The RCM registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus erro...

Page 355: ...y the power on detection logic Because the internal supply voltage was ramping up at the time the low voltage reset LVD status bit is also set to indicate that the reset occurred while the internal su...

Page 356: ...used by LVD trip or POR 1 Reset caused by LVD trip or POR 0 WAKEUP Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakag...

Page 357: ...s a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM AP Control Register 0 Reset not caused by host debugger system setting of the System Reset Requ...

Page 358: ...should be reconfigured before clearing PMC_REGSC ACKISO 0 All filtering disabled 1 LPO clock filter enabled RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is...

Page 359: ...ount is 12 01100 Bus clock filter count is 13 01101 Bus clock filter count is 14 01110 Bus clock filter count is 15 01111 Bus clock filter count is 16 10000 Bus clock filter count is 17 10001 Bus cloc...

Page 360: ...m function is targeted at the manipulation of n bit fields in peripheral registers and is consistent with I O hardware addressing in the Embedded C standard For most BME commands a single core read or...

Page 361: ...iagram As shown in the block diagram the BME module interfaces to a crossbar switch AHB slave port as its primary input and sources an AHB bus output to the Peripheral Bridge PBRIDGE controller The BM...

Page 362: ...a crossbar slave AHB system bus port BME responds strictly on the basis of memory addresses for accesses to the peripheral bridge bus controller All functionality associated with the BME module resid...

Page 363: ...converted into an atomic read modify write that is an indivisible read followed by a write bus sequence Consider decorated store operations first then decorated loads 13 3 1 BME decorated stores The f...

Page 364: ...s translated into a read operation on the output bus using the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 2nd AHB address phase Write access with the...

Page 365: ...ation and mem_addr 19 0 specifies the address offset into the space based at 0x4000_0000 for peripherals The indicates an address bit don t care The decorated AND write operation is defined in the fol...

Page 366: ...t The core performs the required write data lane replication on byte and halfword transfers ioorb 0 0 0 1 mem_addr ioorh 0 0 0 1 mem_addr ioorw 0 0 0 1 mem_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1...

Page 367: ...operation and can be byte 8 bit halfword 16 bit or word 32 bit The core performs the required write data lane replication on byte and halfword transfers ioxorb 0 0 1 mem_addr ioxorh 0 0 1 mem_addr iox...

Page 368: ...idth is 16 bits The core performs the required write data lane replication on byte and halfword transfers The BFI operation can be used to insert a single bit into a peripheral For this case the w fie...

Page 369: ...egister 7 0 xy_z then destination is abxy_zfgh if b 4 and the decorated store strb Rt register 7 0 xyz_ then destination is axyz_efgh if b 5 and the decorated store strb Rt register 7 0 xyz _ then des...

Page 370: ...the second AHB data phase as the original read data is returned to the processor core For an unsigned bit field extract the decorated load transaction is stalled for one cycle in the BME as the data...

Page 371: ...t bus is translated into a read operation on the output bus with the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 second AHB address phase Write access...

Page 372: ...ext rdata Figure 13 8 Decorated load unsigned bit field insert timing diagram The decorated unsigned bit field extract follows the same execution template shown in the above figure a 2 cycle read oper...

Page 373: ...he operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 374: ...o filled in the operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit iolaslb 0 0 1 mem_addr iolaslh 0 0 1 mem_addr iolaslw...

Page 375: ...ht justified and zero filled in the operand returned to the core Recall this is the only decorated operation that does not perform a memory write that is UBFX only performs a read The data size is spe...

Page 376: ...ry Decode decoration Capture address attributes Idle AHB address phase next BME AHB_dp previous Perform memory read Form bit mask Form rdata mask and capture destination data in register Logically rig...

Page 377: ...ferences to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000 0x5000_0000 0x5FFF_FFFF Decorated BFI UBFX references to peripherals and GPIO only based at 0x4000_F000 13 4 Application inf...

Page 378: ...rb r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORW ADDR WDATA __asm ldr r3 3 26 orr r3 addr mov r2 wdata str r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORH ADDR WDATA __asm ldr r3 3 26 orr r3...

Page 379: ...Application information MKW01Z128 MCU Reference Manual Rev 3 04 2016 248 Freescale Semiconductor Inc...

Page 380: ...ossbar master arbitration policy selection Flash controller speculation buffer and cache configurations 14 2 Memory map register descriptions The memory map and register descriptions found here descri...

Page 381: ...lave connections to the device s crossbar switch Address F000_3000h base 8h offset F000_3008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 MCM_PLASC...

Page 382: ...s master connection to AXBS input port n is absent 1 A bus master connection to AXBS input port n is present 14 2 3 Platform Control Register MCM_PLACR The PLACR register selects the arbitration polic...

Page 383: ...h offset F000_300Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 ESFC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DFCS EFDS DFCC DFCIC DFCDA 0 ARB 0...

Page 384: ...14 EFDS Enable Flash Data Speculation Enables flash data speculation 0 Disable flash data speculation 1 Enable flash data speculation 13 DFCC Disable Flash Controller Cache Disables flash controller c...

Page 385: ...read only field is reserved and always has the value 0 2 CPOWOI Compute Operation Wake up on Interrupt 0 No effect 1 When set the CPOREQ is cleared on any interrupt or exception vector fetch 1 CPOACK...

Page 386: ...d descriptions continued Field Description 0 Request is cleared 1 Request Compute Operation Chapter 14 Miscellaneous Control Module MCM MKW01Z128 MCU Reference Manual Rev 3 04 2016 Freescale Semicondu...

Page 387: ...Memory map register descriptions MKW01Z128 MCU Reference Manual Rev 3 04 2016 256 Freescale Semiconductor Inc...

Page 388: ...RAM controller manages requests from two sources AMBA AHB reads and writes from the system bus program trace packet writes from the processor As part of the MTB functionality there is a DWT Data Watc...

Page 389: ...e port from the processor core The private MTB port signals the instruction address information needed for the 64 bit program trace packets written into the system RAM The PRAM controller output inter...

Page 390: ...econd higher addressed word contains the destination of the branch the address it branched to The value stored only records bits 31 1 of the branch address The least significant bit of the value is th...

Page 391: ...s to approximately 1600 processor cycles per KB This metric is obviously very sensitive to the runtime characteristics of the user code The MTB_DWT function not shown in the core platform block diagra...

Page 392: ...propriate crossbar slave port plus the private execution trace bus from the processor core The signals in the private execution trace bus are detailed in the following table taken from the ARM CoreSig...

Page 393: ...ations Attempting to access these locations can result in UNPREDICTABLE behavior The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN reset values are not programmed prior to enablin...

Page 394: ...4 32 R See section 15 3 1 14 274 F000_0FD4 Peripheral ID Register MTB_PERIPHID5 32 R See section 15 3 1 14 274 F000_0FD8 Peripheral ID Register MTB_PERIPHID6 32 R See section 15 3 1 14 274 F000_0FDC P...

Page 395: ...00 In this configuration the MTB_POSITION register is initialized to 0x2000_0000 0x0000_7FF8 0x0000_00000 Following these two suggested placements provides a full featured circular memory buffer conta...

Page 396: ...2 are RAZ WI Therefore the active bits in this field are POSITION 14 3 POSITION POINTER 11 0 2 WRAP WRAP This field is set to 1 automatically when the POINTER value wraps as determined by the MTB_MAST...

Page 397: ...because MTB_FLOW WATERMARK is set then it is not automatically set to 1 if TSTARTEN is 1 and the TSTART input is HIGH In this case tracing can only be restarted if MTB_FLOW WATERMARK or MTB_POSITION...

Page 398: ...0 and the MTB_POSITION 14 MASK 3 MTB_POSITION POINTER 11 MASK 1 bits remain unchanged This field causes the trace packet information to be stored in a circular buffer of size 2 MASK 4 bytes that can b...

Page 399: ...MARK field value actions defined by the AUTOHALT and AUTOSTOP bits are performed 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 AUTOHALT AUTOHALT If th...

Page 400: ...ADDR BASEADDR This value is defined with a hardwired signal and the expression 0x2000_0000 RAM_Size 4 For example if the total RAM capacity is 16 KB this field is 0x1FFF_F000 15 3 1 5 Integration Mode...

Page 401: ...000 15 3 1 7 Claim TAG Clear Register MTB_TAGCLEAR The read write Claim Tag Clear Register is used to read the claim status on debug resources A read indicates the claim tag status Writing 1 to a spec...

Page 402: ...ster It is hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FB4h offset F000_0FB4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 403: ...nly field is reserved and always has the value 0 3 Reserved BIT3 This read only field is reserved and always has the value 1 2 BIT2 BIT2 Connected to NIDEN or DBGEN signal 1 Reserved BIT1 This read on...

Page 404: ...EVICECFG field descriptions Field Description DEVICECFG DEVICECFG Hardwired to 0x0000_0000 15 3 1 13 Device Type Identifier Register MTB_DEVICETYPID This register indicates the device type ID It is ha...

Page 405: ...nt ID Register MTB_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FF...

Page 406: ...ter MTBDWT_DEVICETYPID 32 R 0000_0004h 15 3 2 8 283 F000_1FD0 Peripheral ID Register MTBDWT_PERIPHID4 32 R See section 15 3 2 9 284 F000_1FD4 Peripheral ID Register MTBDWT_PERIPHID5 32 R See section 1...

Page 407: ...5 NOCYCCNT 1 cycle counter is not supported MTBDWT_CTRL 24 NOPRFCNT 1 profiling counters are not supported MTBDWT_CTRL 22 CYCEBTENA 0 no POSTCNT underflow packets generated MTBDWT_CTRL 21 FOLDEVTENA 0...

Page 408: ...TB_MASTER MASK Address F000_1000h base 24h offset 16d i where i 0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MASK W Reset 0 0 0 0 0 0 0 0 0 0...

Page 409: ...Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MATCHED 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DATAVADDR0 DATAVSIZE 0 DATAVMATCH 0 FUNCTION W R...

Page 410: ...word 10 Word 11 Reserved Any attempts to use this value results in UNPREDICTABLE behavior 9 Reserved This field is reserved This read only field is reserved and always has the value 0 8 DATAVMATCH Dat...

Page 411: ...0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FUNCTION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_FCT1 field descriptions Field Description 31 25 Reserved This field is reser...

Page 412: ...to use this value results in UNPREDICTABLE behavior 15 3 2 6 MTB_DWT Trace Buffer Control Register MTBDWT_TBCTRL The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the actual t...

Page 413: ...on of MTBDWT_FCT1 MATCHED 1 Trigger TSTART based on the assertion of MTBDWT_FCT1 MATCHED 0 ACOMP0 Action based on Comparator 0 match When the MTBDWT_FCT0 MATCHED is set it indicates MTBDWT_COMP0 addre...

Page 414: ...ICECFG DEVICECFG Hardwired to 0x0000_0000 15 3 2 8 Device Type Identifier Register MTBDWT_DEVICETYPID This register indicates the device type ID It is hardwired to specific values used during the auto...

Page 415: ...nent ID Register MTBDWT_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_1000h ba...

Page 416: ...PUID Debug control Data watchpoint unit CoreSight ID Watchpoint control Breakpoint unit CoreSight ID Breakpoint control Optional component Figure 15 3 CoreSight discovery process ROM memory map Absolu...

Page 417: ...nent ID Register ROM_COMPID1 32 R See section 15 3 3 5 288 F000_2FF8 Component ID Register ROM_COMPID2 32 R See section 15 3 3 5 288 F000_2FFC Component ID Register ROM_COMPID3 32 R See section 15 3 3...

Page 418: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM_TABLEMARK field descriptions Field Description MARK MARK Hardwired to 0x0000_0000 15 3 3 3 System Access Register ROM_SYSACCESS This register indicates syste...

Page 419: ...0x0000_0008 and all the others to 0x0000_0000 15 3 3 5 Component ID Register ROM_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery...

Page 420: ...e This structure allows up to four bus masters to access different bus slaves simultaneously while providing arbitration among the bus masters when they access the same slave 16 1 1 Features The cross...

Page 421: ...e master device has no knowledge of whether it actually owns the slave port it is targeting While the master does not have control of the slave port it is targeting it simply waits After the master ha...

Page 422: ...r details on slot assignments The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals 17 1 1 Features Key features of the peripheral bridge are Support...

Page 423: ...32 R W See section 17 2 3 300 54 Peripheral Access Control Register AIPS_PACRJ 32 R W See section 17 2 3 300 58 Peripheral Access Control Register AIPS_PACRK 32 R W See section 17 2 3 300 5C Periphera...

Page 424: ...es whether the master is trusted for read accesses 0 This master is not trusted for read accesses 1 This master is trusted for read accesses 29 MTW0 Master 0 Trusted For Writes Determines whether the...

Page 425: ...ster 3 Trusted For Writes Determines whether the master is trusted for write accesses 0 This master is not trusted for write accesses 1 This master is trusted for write accesses 16 MPL3 Master 3 Privi...

Page 426: ...ACR100 PACR101 PACR102 PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C PACRP PACR120...

Page 427: ...1 Accesses from an untrusted master are not allowed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 SP1 Supervisor Protect Determines whether the per...

Page 428: ...owed 1 Accesses from an untrusted master are not allowed 19 Reserved This field is reserved This read only field is reserved and always has the value 0 18 SP3 Supervisor Protect Determines whether the...

Page 429: ...lowed 1 Accesses from an untrusted master are not allowed 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 SP5 Supervisor Protect Determines whether th...

Page 430: ...master are allowed 1 Accesses from an untrusted master are not allowed 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 SP7 Supervisor Protect Determines...

Page 431: ...the master privilege level must indicate the supervisor access attribute and the MPRx MPLn control field for the master must be set If not access terminates with an error response and no peripheral ac...

Page 432: ...lowed 1 Accesses from an untrusted master are not allowed 23 Reserved This field is reserved This read only field is reserved and always has the value 0 22 SP2 Supervisor Protect Determines whether th...

Page 433: ...allowed 1 Accesses from an untrusted master are not allowed 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 SP4 Supervisor Protect Determines whether...

Page 434: ...wed 1 Accesses from an untrusted master are not allowed 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 SP6 Supervisor Protect Determines whether the pe...

Page 435: ...tected 0 TP7 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master When this field is set and an access is attempted by an untrusted master the access terminates w...

Page 436: ...of this module s instances see the chip configuration information 18 1 1 Overview The Direct Memory Access Multiplexer DMAMUX routes DMA sources called slots to any of the four DMA channels This proce...

Page 437: ...r always on slots can be routed to four channels four independently selectable DMA channel routers The first two channels additionally provide a trigger functionality Each channel router can be assign...

Page 438: ...rupt timer PIT This mode is available only for channels 0 1 18 2 External signal description The DMAMUX has no external pins 18 3 Memory map register definition This section provides a detailed descri...

Page 439: ...hannel 0 Triggering is disabled If triggering is disabled and ENBL is set the DMA Channel will simply route the specified source to the DMA channel Normal mode 1 Triggering is enabled If triggering is...

Page 440: ...or packets at fixed intervals without the need for processor intervention The trigger is generated by the periodic interrupt timer PIT as such the configuration of the periodic triggering interval is...

Page 441: ...s been seen This is illustrated in the following figure DMA request Peripheral request Trigger Figure 18 3 DMAMUX channel triggering normal operation After the DMA request has been serviced the periph...

Page 442: ...hod to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO ports to drive or sample waveforms By configuring the DMA to tran...

Page 443: ...re software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions of the...

Page 444: ...d before use 18 5 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 2 DMA channel...

Page 445: ...channel 3 Write 0x85 to CHCFG1 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits v...

Page 446: ...eps 2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMAMUX_BASE_ADDR 0x0...

Page 447: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information MKW01Z128 MCU Reference Manual Rev 3 04 2016 316 Freescale Semiconductor Inc...

Page 448: ...is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels DMA0 DMA1 DMA2 or DMA3 19 1 1 Overview The DMA controller module enables fast tr...

Page 449: ...3 Addr Attr Interrupts Phase Bus Signals Current Master Attributes Write Data Bus Read Data Bus System Bus Address System Bus Size SysBus Interface MUX SysBus Interface Registered Addr DACK2 DACK1 DAC...

Page 450: ...The DMA module consists of four independent functionally equivalent channels so references to DMA in this chapter apply to any of the channels It is not possible to address all four channels at once...

Page 451: ...he operation is finished successfully or due to an error The channel indicates the operation status in the channel s DSR described in the definitions of the DMA Status Registers DSRn and Byte Count Re...

Page 452: ...Control Register DMA_DCR2 32 R W 0000_0000h 19 3 4 325 4000_8130 Source Address Register DMA_SAR3 32 R W 0000_0000h 19 3 1 321 4000_8134 Destination Address Register DMA_DAR3 32 R W 0000_0000h 19 3 2...

Page 453: ...itten to bits 31 20 of this register see the value list in the field description A write of any other value to these bits causes a configuration error when the channel starts to execute For more infor...

Page 454: ...mpletion of the write transfer BCRn decrements by 1 2 or 4 for 8 bit 16 bit or 32 bit accesses respectively BCRn is cleared if a 1 is written to DSR DONE In response to an event the DMA controller wri...

Page 455: ...is cleared at hardware reset or by writing a 1 to DONE 0 No bus error occurred 1 The DMA channel terminated with a bus error during the read portion of a transfer 28 BED Bus Error on Destination BED...

Page 456: ...ritten with a value equal to or less than 0F_FFFFh After being written with a value in this range bits 23 20 of BCR read back as 0000b A write to BCR of a value greater than 0F_FFFFh causes a configur...

Page 457: ...source accesses are auto aligned otherwise destination accesses are auto aligned Source alignment takes precedence over destination alignment If auto alignment is enabled the appropriate address regis...

Page 458: ...er size The value of this boundary is based upon the initial source address SAR The base address should be aligned to a 0 modulo circular buffer size boundary Misaligned buffers are not possible The b...

Page 459: ...served This read only field is reserved and always has the value 0 5 4 LINKCC Link Channel Control Allows DMA channels to have their transfers linked The current DMA channel triggers a DMA request to...

Page 460: ...nsfer occurs DSRn CE is set and depending on the DCR configuration an interrupt event may be issued If the auto align bit DCRn AA is set error checking is performed on the appropriate registers A read...

Page 461: ...mation describing configuration request generation method and pointers to the data to be moved 19 4 2 1 Channel prioritization The four DMA channels are prioritized based on number with channel 0 havi...

Page 462: ...ed with the total number of bytes to be transferred It is decremented by 1 2 or 4 at the end of each transfer depending on the transfer size DSRn DONE must be cleared for channel startup After the cha...

Page 463: ...ansfer is initiated if continuous mode is enabled DCRn CS 0 If a termination error occurs DSRn BED DONE are set and DMA transactions stop 19 4 4 Advanced Data Transfer Controls Auto Alignment Typicall...

Page 464: ...st size allowed based on the address but not exceeding the configured size 19 4 5 Termination An unsuccessful transfer can terminate for one of the following reasons Error conditions When the DMA enco...

Page 465: ...Functional Description MKW01Z128 MCU Reference Manual Rev 3 04 2016 334 Freescale Semiconductor Inc...

Page 466: ...clock internal or external as a source for the MCU system clock The MCG operates in conjuction with a crystal oscillator which allows an external crystal ceramic resonator or another external clock so...

Page 467: ...IRC can be used as the FLL source Either the slow or the fast clock can be selected as the clock source for the MCU Can be used as a clock source for other on chip peripherals Control signals for the...

Page 468: ...for other on chip peripherals MCG Fixed Frequency Clock MCGFFCLK is provided as a clock source for other on chip peripherals MCG Internal Reference Clock MCGIRCLK is provided as a clock source for oth...

Page 469: ...0h 20 3 6 344 4006_4006 MCG Status Register MCG_S 8 R 10h 20 3 7 345 4006_4008 MCG Status and Control Register MCG_SC 8 R W 02h 20 3 8 347 4006_400A MCG Auto Trim Compare Value High Register MCG_ATCVH...

Page 470: ...Factor is 8 for all other RANGE 0 values Divide Factor is 256 100 If RANGE 0 0 or OSCSEL 1 Divide Factor is 16 for all other RANGE 0 values Divide Factor is 512 101 If RANGE 0 0 or OSCSEL 1 Divide Fa...

Page 471: ...e the Oscillator OSC chapter for more details and the device data sheet for the frequency ranges used 00 Encoding 0 Low frequency range selected for the crystal oscillator 01 Encoding 1 High frequency...

Page 472: ...binary weighted that is bit 1 adjusts twice as much as bit 0 Increasing the binary value increases the period and decreasing the value decreases the period An additional fine trim bit is available in...

Page 473: ...Frequency Range table for more details 00 Encoding 0 Low range reset default 01 Encoding 1 Mid range 10 Encoding 2 Mid high range 11 Encoding 3 High range 4 1 FCTRIM Fast Internal Reference Clock Tri...

Page 474: ...PLL Stop Enable Enables the PLL Clock during Normal Stop In Low Power Stop mode the PLL clock gets disabled even if PLLSTEN 0 1 All other power modes PLLSTEN 0 bit has no affect and does not enable th...

Page 475: ...as the MCG source when CLKS 1 0 00 If the PLLS bit is cleared and PLLCLKEN 0 is not set the PLL is disabled in all modes If the PLLS is set the FLL is disabled in all modes 0 FLL is selected 1 PLL is...

Page 476: ...42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 20 3 7...

Page 477: ...utput clock 4 IREFST Internal Reference Status This bit indicates the current source for the FLL reference clock The IREFST bit does not update immediately after a write to the IREFS bit due to intern...

Page 478: ...nternal Reference Clock selected 1 4 MHz Internal Reference Clock selected 5 ATMF Automatic Trim Machine Fail Flag Fail flag for the Automatic Trim Machine ATM This bit asserts when the Automatic Trim...

Page 479: ...red The LOCS0 bit only has an effect when CME0 is set This bit is cleared by writing a logic 1 to it when set 0 Loss of OSC0 has not occurred 1 Loss of OSC0 has occurred 20 3 9 MCG Auto Trim Compare V...

Page 480: ...erved and always has the value 0 5 2 Reserved Reserved This field is reserved This read only field is reserved and always has the value 0 1 Reserved Reserved This field is reserved This read only fiel...

Page 481: ...ld is reserved This read only field is reserved and always has the value 0 0 Reserved This field is reserved This read only field is reserved and always has the value 0 20 3 13 MCG Control 10 Register...

Page 482: ...lue 0 20 3 14 MCG Test 3 Register MCG_T3 Address 4006_4000h base 13h offset 4006_4013h Bit 7 6 5 4 3 2 1 0 Read 0 Write Reset 0 0 0 0 0 0 0 0 MCG_T3 field descriptions Field Description Reserved This...

Page 483: ...t to PBE clock mode and the C1 CLKS and S CLKST will automatically be set to 2 b10 If entering Normal Stop mode when the MCG is in PEE mode with PLLSTEN 0 the MCG will reset to PBE clock mode and C1 C...

Page 484: ...iption for more details In FEE mode the PLL is disabled in a low power state unless C5 PLLCLKEN is set FLL Bypassed Internal FBI FLL bypassed internal FBI mode is entered when all the following condit...

Page 485: ...hen all the following conditions occur 10 is written to C1 CLKS 0 is written to C1 IREFS 1 is written to C6 PLLS 0 is written to C2 LP In PBE mode MCGOUTCLK is derived from the OSCSEL external referen...

Page 486: ...Stop mode from PEE mode and if C5 PLLSTEN 0 on exit the MCG clock mode is forced to PBE mode the C1 CLKS and S CLKST will be configured to 2 b10 and S LOCK bit will clear without setting S LOLS If C5...

Page 487: ...e for other on chip peripherals and is enabled when C1 IRCLKEN 1 When enabled MCGIRCLK is driven by either the fast internal reference clock 4 MHz IRC which can be divided down by the FRDIV factors or...

Page 488: ...d the PLL LOCK status bit is cleared 20 4 5 MCG Fixed Frequency Clock The MCG Fixed Frequency Clock MCGFFCLK provides a fixed frequency clock source for other on chip peripherals see the block diagram...

Page 489: ...l reference clock such as FBE clock mode The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock The bus clock is also required to be running w...

Page 490: ...re lock in tfll_acquire milliseconds 20 5 1 1 Initializing the MCG Because the MCG comes out of reset in FEI mode the only MCG modes that can be directly switched to upon reset are FEE FBE and FBI mod...

Page 491: ...lized If in FEE mode check to make sure S IREFST is cleared before moving on If in FBE mode check to make sure S IREFST is cleared and S CLKST bits have changed to 2 b10 indicating the external refere...

Page 492: ...MHz 5 Wait for the FLL lock time to guarantee FLL is running at new C4 DRST_DRS and C4 DMX32 programmed frequency To change from FEI clock mode to FBI clock mode follow this procedure 1 Change C1 CLKS...

Page 493: ...OSCINIT must be checked before moving on in the application software Additionally care must be taken to ensure that the reference clock divider C1 FRDIV and C5 PRDIV0 is set properly for the mode bein...

Page 494: ...rystal If using an external clock source less than 2 MHz the MCG must not be configured for any of the PLL modes PEE and PBE 20 5 3 1 Example 1 Moving from FEI to PEE mode External Crystal 4 MHz MCGOU...

Page 495: ...BE mode a BLPE If a transition through BLPE mode is desired first set C2 LP to 1 b BLPE PBE C6 0x40 C6 PLLS set to 1 selects the PLL At this time with a C1 PRDIV value of 2 b001 the PLL reference divi...

Page 496: ...rce b Loop until S CLKST are 2 b11 indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode Now with PRDIV of divide by 2 and C6 VDIV of multiply by 24 MCGOUTCLK 4 MHz 2...

Page 497: ...LPE MODE C2 0x1E C2 LP 1 CHECK CHECK C1 0x10 CHECK CONTINUE IN PEE MODE S PLLST 1 S LOCK 1 S CLKST 10 S CLKST 11 S LP 1 S IREFST 0 S OSCINIT 1 C5 0x01 C5 VDIV 1 Figure 20 3 Flowchart of FEI to PEE mod...

Page 498: ...ired first set C2 LP to 1 b BLPE FBE C6 0x00 C6 PLLS clear to 0 to select the FLL At this time with C1 FRDIV value of 3 b010 the FLL divider is set to 128 resulting in a reference frequency of 4 MHz 1...

Page 499: ...ed as the reference clock source c Loop until S CLKST are 2 b01 indicating that the internal reference clock is selected to feed MCGOUTCLK 4 Lastly FBI transitions into BLPI mode a C2 0x02 C2 LP is 1...

Page 500: ...REFST 0 CHECK S CLKST 01 YES NO YES C2 LP 1 C6 0x00 IN BLPE MODE IN BLPE MODE NO YES C2 0x1C C2 LP 0 C2 0x1E ENTER BLPE MODE C2 LP 1 Figure 20 4 Flowchart of PEE to BLPI mode transition using an 4 MHz...

Page 501: ...Initialization Application information MKW01Z128 MCU Reference Manual Rev 3 04 2016 370 Freescale Semiconductor Inc...

Page 502: ...MHz 8 32 MHz crystals and resonators High Range mode Automatic Gain Control AGC to optimize power consumption in high frequency ranges 3 8 MHz 8 32 MHz using low power mode High gain option in freque...

Page 503: ...ailable for the OSC module Refer to signal multiplexing information for this MCU for more details Table 21 1 OSC Signal Descriptions Signal Description I O EXTAL External clock Oscillator input I XTAL...

Page 504: ...Therefore the feedback resistor must not be externally with the Connection 3 OSC EXTAL Crystal or Resonator VSS XTAL Figure 21 2 Crystal Ceramic Resonator Connections Connection 1 OSC VSS RF Crystal...

Page 505: ...ound here NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it OSC VSS Clock Input I O XTAL EXTAL Figure 21 5 External Clock Connections 21 7 Memory Map Register Defin...

Page 506: ...bles external reference clock OSCERCLK 0 External reference clock is inactive 1 External reference clock is enabled 6 Reserved This field is reserved This read only field is reserved and always has th...

Page 507: ...r load 0 Disable the selection 1 Add 8 pF capacitor to the oscillator load 0 SC16P Oscillator 16 pF Capacitor Load Configure Configures the oscillator load 0 Disable the selection 1 Add 16 pF capacito...

Page 508: ...ts 21 8 1 1 Off The OSC enters the Off state when the system does not require OSC clocks Upon entering this state XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by c...

Page 509: ...SC_CLK_OUT Its frequency is determined by the external components being used 21 8 1 4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selection...

Page 510: ...l capacitors could be used 21 8 2 2 Low Frequency Low Power Mode In low frequency low power mode the oscillator uses a gain control loop to minimize power consumption As the oscillation amplitude incr...

Page 511: ...is for voltage filtering and converts the output to logic levels 21 8 3 Counter The oscillator output clock OSC_CLK_OUT is gated off until the counter has detected 4096 cycles of its input clock XTL_C...

Page 512: ...gister settings If CR ERCLKEN and CR EREFSTEN are set before entry to Low Leakage Stop modes the OSC is still functional in these modes After waking up from Very Low Leakage Stop VLLSx modes all OSC r...

Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...

Page 514: ...bit 16 bit and 32 bit read operations from the program flash memory A write operation to program flash memory results in a bus error In addition the FMC provides two separate mechanisms for accelerat...

Page 515: ...s programming model provides control and configuration of the FMC s features For details see the description of the MCM s Platform Control Register PLACR 22 5 Functional description The FMC is a flash...

Page 516: ...example the user may adjust the controls to enable buffering per access type data or instruction NOTE When reconfiguring the FMC do not program the control and configuration inputs to the FMC while t...

Page 517: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 386 Freescale Semiconductor Inc...

Page 518: ...e bits from the 1 state erased to the 0 state programmed Only the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in the era...

Page 519: ...mated built in program and erase algorithms with verify 23 1 1 2 Other Flash Memory Module Features Internal high voltage supply generator for flash memory program and erase operations Optional interr...

Page 520: ...odule which provides the nonvolatile memory storage Flash Memory Module All flash blocks plus a flash management unit providing high level control and an interface to MCU buses IFR Nonvolatile informa...

Page 521: ...from the programming time RWW Read While Write The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource Secure An MCU state conveyed...

Page 522: ...ption byte Refer to the description of the Flash Option Register FOPT 0x0_040C 1 Flash security byte Refer to the description of the Flash Security Register FSEC 23 3 2 Program Flash IFR Map The progr...

Page 523: ...this initialization period the user may write any register All register writes are also disabled except for registers FCNFG and FSTAT whenever an erase suspend request is active FCNFG ERSSUSP 1 FTFA...

Page 524: ...A_FCCOB8 8 R W 00h 23 3 3 5 398 4002_0010 Program Flash Protection Registers FTFA_FPROT3 8 R W Undefined 23 3 3 6 399 4002_0011 Program Flash Protection Registers FTFA_FPROT2 8 R W Undefined 23 3 3 6...

Page 525: ...Error Flag Indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command While ACCERR is set the CCIF fla...

Page 526: ...pt enabled An interrupt request is generated whenever the FSTAT CCIF flag is set 6 RDCOLLIE Read Collision Error Interrupt Enable Controls interrupt generation when a flash memory read collision error...

Page 527: ...y field is reserved and always has the value 0 23 3 3 3 Flash Security Register FTFA_FSEC This read only register holds all bits associated with the security of the MCU and flash memory module During...

Page 528: ...matter 00 NXP factory access granted 01 NXP factory access denied 10 NXP factory access denied 11 NXP factory access granted SEC Flash Security Defines the security state of the MCU In the secure stat...

Page 529: ...mpose the FCCOB data set can be written in any order but you must provide all needed values which vary from command to command First set up all required FCCOB fields and then initiate the command s ex...

Page 530: ...bytes 23 3 3 6 Program Flash Protection Registers FTFA_FPROTn The FPROT registers define which program flash regions are protected from program and erase operations Protected flash regions cannot have...

Page 531: ...sh Configuration Field Then reprogram the program flash protection byte Address 4002_0000h base 10h offset 1d i where i 0d to 3d Bit 7 6 5 4 3 2 1 0 Read PROT Write Reset x x x x x x x x Notes x Undef...

Page 532: ...register represents 1 32 of the total program flash except for memory configurations with less than 32 KB of program flash where each assigned bit protects 1 KB 0 Program flash region is protected 1 P...

Page 533: ...escribed in the application note are available on this device 23 4 2 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events These int...

Page 534: ...the MCU is allowed to enter stop mode CAUTION The MCU should never enter stop mode while any flash command is running CCIF 0 NOTE While the MCU is in very low power modes VLPR VLPW VLPS the flash memo...

Page 535: ...heral bus writes The user cannot initiate any further flash commands until notified that the current command has completed The flash command structure and operation are detailed in Flash Command Opera...

Page 536: ...nd from launching can t clear FSTAT CCIF if the previous command resulted in an access error FSTAT ACCERR 1 or a protection violation FSTAT FPVIOL 1 In error scenarios two writes to FSTAT are required...

Page 537: ...STAT MGSTAT0 A command may have access errors protection errors and run time errors but the run time errors are not seen until all access and protection errors have been corrected 3 Command execution...

Page 538: ...vious command complete no CCIF 1 yes START CCIF 1 Read FSTAT register no yes Bit Polling for Command Completion Check Figure 23 3 Generic flash command write sequence flowchart 23 4 8 2 Flash Commands...

Page 539: ...x44 Erase All Blocks Erase the program flash block verify erase and release MCU security NOTE An erase is only possible when all memory locations are unprotected 0x45 Verify Backdoor Access Key Releas...

Page 540: ...ary of flash memory devices Erased 1 and programmed 0 bit states can degrade due to elapsed time and data cycling number of times a bit is erased and re programmed The lifetime of the erased states is...

Page 541: ...ing table provided for each command Ensure that FSTAT ACCERR and FSTAT FPVIOL are cleared prior to starting the command write sequence As described in Launch the Command by Clearing CCIF a new command...

Page 542: ...tion operation completes Table 23 4 Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal...

Page 543: ...set FSTAT CCIF is set after the Program Check operation completes The supplied address must be longword aligned the lowest two bits of the byte address must be 00 Byte 3 data is written to the suppli...

Page 544: ...select code as shown in Table 23 10 Table 23 9 Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents 7 0 0 0x03 RDRSRC 1 Flash address 23 16 2 Flash address 15 8 3 Flash address 7 0 1 R...

Page 545: ...ed FSTAT ACCERR 23 4 10 4 Program Longword Command The Program Longword command programs four previously erased bytes in the program flash memory using an embedded algorithm CAUTION A flash memory loc...

Page 546: ...ling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR An invalid flash address is supplied FSTAT ACCERR Flash address is not longword aligned FSTAT ACCERR Flash ad...

Page 547: ...memory module sets CCIF While ERSSUSP is set all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers If an Erase Flash Sector operation effectively completes befo...

Page 548: ...ded Erase Flash Sector operation by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch When a suspended operation is aborted the flash memory module starts the new command usi...

Page 549: ...RSSUSP Execute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR...

Page 550: ...tate The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blocks command If the read fails i e all memory resources are no...

Page 551: ...values for the Read Once command range from 0x00 0x0F During execution of the Read Once command any attempt to read addresses within the program flash block containing the selected record index retur...

Page 552: ...During execution of the Program Once command any attempt to read addresses within the program flash block containing the selected record index returns invalid data Table 23 22 Program Once Command Er...

Page 553: ...ncommanded fashion outside of the flash memory Refer to the device s Chip Configuration details for information on this functionality Before invoking the external erase all function the FSTAT ACCERR a...

Page 554: ...ield If the backdoor keys match the FSEC SEC field is changed to the unsecure state and security is released If the backdoor keys do not match security is not released and all future attempts to execu...

Page 555: ...rther in AN4507 Using the Kinetis Security and Flash Protection Features Note that not all features described in the application note are available on this device Table 23 27 FSEC register fields FSEC...

Page 556: ...kdoor Access Key command is active program flash memory is not available for read access and returns invalid data The user code stored in the program flash memory must have a method of receiving the b...

Page 557: ...et the flash memory module executes a sequence which establishes initial values for the flash block configuration parameters FPROT FOPT and FSEC registers FSTAT CCIF is cleared throughout the reset se...

Page 558: ...16 bit analog to digital converter ADC is a successive approximation ADC designed for operation within an integrated microcontroller system on chip NOTE For the chip specific modes of operation see t...

Page 559: ...rupt Input clock selectable from up to four sources Operation in low power modes for lower noise Asynchronous clock source for lower noise operation with option to output the clock Selectable hardware...

Page 560: ...COFS V REFSH V REFSL SC2 CFG1 CFG2 Conversion trigger control Clock divide Control sequencer Bus clock SAR converter Compare logic Offset subtractor Averager Formatting ADLSMP ADLSTS ADLPC ADHSC initi...

Page 561: ...as VDD External filtering may be necessary to ensure clean VDDA for good results 24 3 2 Analog Ground VSSA The ADC analog portion uses VSSA as its ground connection In some packages VSSA is connected...

Page 562: ...and DADMx referenced to each other to provide the most accurate analog to digital readings A differential input is selected for conversion through SC1 ADCH when SC1n DIFF is high All DADPx inputs may...

Page 563: ...CLP3 32 R W 0000_0100h 24 4 14 448 4003_B044 ADC Plus Side General Calibration Value Register ADC0_CLP2 32 R W 0000_0080h 24 4 15 448 4003_B048 ADC Plus Side General Calibration Value Register ADC0_CL...

Page 564: ...ing SC1A while SC1A is actively controlling a conversion aborts the current conversion In Software Trigger mode when SC2 ADTRG 0 writes to SC1A subsequently initiate a new conversion if SC1 ADCH conta...

Page 565: ...channel select Selects one of the input channels The input channel decode depends on the value of DIFF DAD0 DAD3 are associated with the input pin pairs DADPx and DADMx NOTE Some of the input channel...

Page 566: ...FF 0 AD19 is selected as input when DIFF 1 it is reserved 10100 When DIFF 0 AD20 is selected as input when DIFF 1 it is reserved 10101 When DIFF 0 AD21 is selected as input when DIFF 1 it is reserved...

Page 567: ...he expense of maximum clock speed 6 5 ADIV Clock Divide Select Selects the divide ratio used by the ADC to generate the internal clock ADCK 00 The divide ratio is 1 and the clock rate is input clock 0...

Page 568: ...o be active prior to conversion start When it is selected and it is not active prior to a conversion start when CFG2 ADACKEN 0 the asynchronous clock is activated at the start of a conversion and deac...

Page 569: ...eed Configuration Configures the ADC for very high speed operation The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks 0 Normal c...

Page 570: ...2 bit single ended 0 0 0 0 D D D D D D D D D D D D Unsigned right justified 11 bit differential S S S S S S D D D D D D D D D D Sign extended 2 s complement 10 bit single ended 0 0 0 0 0 0 D D D D D D...

Page 571: ...are related to the ADC mode of operation The compare value 2 register CV2 is used only when the compare range function is enabled that is SC2 ACREN 1 Address 4003_B000h base 18h offset 4d i where i 0...

Page 572: ...0 0 0 ADCx_SC2 field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 ADACT Conversion Active Indicates that a conversi...

Page 573: ...tionality based on the values placed in CV1 and CV2 3 ACREN Compare Function Range Enable Configures the compare function to check if the conversion result of the input being monitored is either betwe...

Page 574: ...hile the calibration is in progress and is cleared when the calibration sequence is completed CALF must be checked to determine the result of the calibration sequence Once started the calibration rout...

Page 575: ...ples averaged 10 16 samples averaged 11 32 samples averaged 24 4 8 ADC Offset Correction Register ADCx_OFS The ADC Offset Correction Register OFS contains the user selected or calibration generated of...

Page 576: ...4003_B000h base 2Ch offset 4003_B02Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0...

Page 577: ...ion values of varying widths CLP0 5 0 CLP1 6 0 CLP2 7 0 CLP3 8 0 CLP4 9 0 CLPS 5 0 and CLPD 5 0 CLPx are automatically set when the self calibration sequence is done that is CAL is cleared If these re...

Page 578: ...LPS Calibration Value Calibration Value 24 4 13 ADC Plus Side General Calibration Value Register ADCx_CLP4 For more information see CLPD register description Address 4003_B000h base 3Ch offset 4003_B0...

Page 579: ...0 CLP3 Calibration Value Calibration Value 24 4 15 ADC Plus Side General Calibration Value Register ADCx_CLP2 For more information see CLPD register description Address 4003_B000h base 44h offset 400...

Page 580: ...LP1 Calibration Value Calibration Value 24 4 17 ADC Plus Side General Calibration Value Register ADCx_CLP0 For more information see CLPD register description Address 4003_B000h base 4Ch offset 4003_B0...

Page 581: ...dress 4003_B000h base 54h offset 4003_B054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 582: ...10 Reserved This field is reserved This read only field is reserved and always has the value 0 CLM4 Calibration Value Calibration Value 24 4 21 ADC Minus Side General Calibration Value Register ADCx_...

Page 583: ...d only field is reserved and always has the value 0 CLM2 Calibration Value Calibration Value 24 4 23 ADC Minus Side General Calibration Value Register ADCx_CLM1 For more information see CLMD register...

Page 584: ...clock output enable is disabled or CFG2 ADACKEN 0 the module is in its lowest power state The ADC can perform an analog to digital conversion on any of the software selectable channels All modes perfo...

Page 585: ...clock source within the ADC module When the ADACK clock source is selected it is not required to be active prior to conversion start When it is selected and it is not active prior to a conversion sta...

Page 586: ...available and hardware trigger is enabled that is SC2 ADTRG 1 a conversion is initiated on the rising edge of ADHWT after a hardware trigger select event that is ADHWTSn has occurred If a conversion...

Page 587: ...y CFG1 MODE and SC1n DIFF as shown in the description of CFG1 MODE Conversions can be initiated by a software or hardware trigger In addition the ADC module can be configured for Low power operation L...

Page 588: ...gered operation conversions begin after SC1A is written In hardware triggered operation conversions begin after a hardware trigger If continuous conversions are also enabled a new set of conversions t...

Page 589: ...Stop mode with ADACK or Alternate Clock Sources not enabled When a conversion is aborted the contents of the data registers Rn are not altered The data registers continue to be the values transferred...

Page 590: ...onfiguration that is CFG2 ADHSC The frequency of the conversion clock that is fADCK CFG2 ADHSC is used to configure a higher clock input frequency This will allow faster overall conversion times To me...

Page 591: ...dder SFCAdder 1 x 0x 10 3 ADCK cycles 5 bus clock cycles 1 1 11 3 ADCK cycles 5 bus clock cycles1 1 0 11 5 s 3 ADCK cycles 5 bus clock cycles 0 x 0x 10 5 ADCK cycles 5 bus clock cycles 0 1 11 5 ADCK c...

Page 592: ...DCK cycles Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications 24 5 4 6 Conversion time examples The following examples use the Equation 1 on page 460 an...

Page 593: ...guration A configuration for long ADC conversion is 16 bit differential mode with the bus clock selected as the input clock source The input clock divide by 8 ratio selected Bus frequency of 8 MHz Lon...

Page 594: ...CK cycles 5 bus clock cycles AverageNum 1 BCT 17 ADCK cycles LSTAdder 0 ADCK cycles HSCAdder 2 The resulting conversion time is generated using the parameters listed in in the preceding table Therefor...

Page 595: ...he input is sampled and converted the compare values in CV1 and CV2 are used as described in the following table There are six Compare modes as shown in the following table Table 24 11 Compare modes S...

Page 596: ...hile the MCU is in Wait or Normal Stop modes The ADC interrupt wakes the MCU when the compare condition is met 24 5 6 Calibration function The ADC contains a self calibration function that is required...

Page 597: ...ear and SC3 CALF to set At the end of a calibration sequence SC1n COCO will be set SC1n AIEN can be used to allow an interrupt to occur at the end of a calibration sequence At the end of the calibrati...

Page 598: ...de of operation The formatting of the OFS is different from the data result register Rn to preserve the resolution of the calibration value regardless of the conversion mode selected Lower order bits...

Page 599: ...e user defined offset For applications that may change the offset repeatedly during operation store the initial offset calibration value in flash so it can be recovered and added to any user offset ad...

Page 600: ...CK are available as conversion clock sources while in Wait mode The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU See the Chip Configuratio...

Page 601: ...from Normal Stop mode if the respective ADC interrupt is enabled that is when SC1n AIEN 1 The result register Rn will contain the data from the first completed conversion that occurred during Normal S...

Page 602: ...complete conversions an initialization procedure must be performed A typical sequence is 1 Calibrate the ADC by following the calibration instructions in Calibration function 2 Update CFG to select th...

Page 603: ...ACT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3 ACREN 0 Compare range di...

Page 604: ...edded control applications requiring an ADC For guidance on selecting optimum external component values and converter parameters see AN4373 Cookbook for SAR ADC Measurements 24 7 1 External pins and r...

Page 605: ...ference The two pairs are external VREFH and VREFL and alternate VALTH and VALTL These voltage references are selected using SC2 REFSEL The alternate voltage reference pair VALTH and VALTL may select...

Page 606: ...etween VREFH and VREFL If the input is equal to or exceeds VREFH the converter circuit converts the signal to 0xFFF which is full scale 12 bit representation 0x3FF which is full scale 10 bit represent...

Page 607: ...it mode 12 in 12 bit mode or 16 in 16 bit mode 24 7 2 3 Noise induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion The ADC accuracy...

Page 608: ...ime error Reduce the effect of synchronous noise by operating off the asynchronous clock that is ADACK and averaging Noise that is synchronous to ADCK cannot be averaged out 24 7 2 4 Code width and qu...

Page 609: ...fferential non linearity DNL This error is defined as the worst case difference between the actual code width and the ideal code width for all conversions Integral non linearity INL This error is defi...

Page 610: ...city occurs when except for code jitter the converter converts to a lower code for a higher input voltage Missing codes Missing codes are those values never converted for any input value In 8 bit or 1...

Page 611: ...Application information MKW01Z128 MCU Reference Manual Rev 3 04 2016 480 Freescale Semiconductor Inc...

Page 612: ...full range of the supply voltage The 6 bit DAC is 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed The 64 tap resistor la...

Page 613: ...delay at the expense of higher power Low power with longer propagation delay DMA transfer support A comparison event can be selected to trigger a DMA transfer Functional in all modes of operation The...

Page 614: ...re supply range 25 1 4 CMP DAC and ANMUX diagram The following figure shows the block diagram for the High Speed Comparator DAC and ANMUX modules Chapter 25 Comparator CMP MKW01Z128 MCU Reference Manu...

Page 615: ...0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INM Sample input Figure 25 1 CMP DAC and ANMUX block diagram 25 1 5 CMP block diagram...

Page 616: ...assed when not in use The Filter block acts as a simple sampler if the filter is bypassed and CR0 FILTER_CNT is set to 0x01 The Filter block filters based on multiple samples when the filter is bypass...

Page 617: ...samples that must agree prior to the comparator ouput filter accepting a new output state For information regarding filter programming and latency see the Functional description 000 Filter is disable...

Page 618: ...he CMP should be enabled If the DAC is to be used as a reference to the CMP it should also be enabled CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6 bit DA...

Page 619: ...the pin If the comparator does not own the field this bit has no effect 0 EN Comparator Module Enable Enables the Analog Comparator module When the module is not enabled it remains in the off state an...

Page 620: ...will be asserted when CFR is set 0 Interrupt is disabled 1 Interrupt is enabled 3 IEF Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP When this field is set an interrupt wi...

Page 621: ...s powered down to conserve power 0 DAC is disabled 1 DAC is enabled 6 VRSEL Supply Voltage Reference Source Select 0 Vin1 is selected as resistor ladder network supply reference 1 Vin2 is selected as...

Page 622: ...g a noise generator 000 IN0 001 IN1 010 IN2 011 IN3 100 IN4 101 IN5 110 IN6 111 IN7 MSEL Minus Input Mux Control Determines which input is selected for the minus input of the comparator For INx inputs...

Page 623: ...lter and sampling features can be combined as shown in the following table Individual modes are discussed below Table 25 1 Comparator sample filter controls Mode CR1 EN CR1 WE CR1 SE CR0 FILTER_C NT F...

Page 624: ...INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 1 WE 0 SE CGMUX COS FILT_PER 0 FILT_PER COS IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO bus clock To other syste...

Page 625: ...ive The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block clock input The com...

Page 626: ...EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt control Clock prescaler To other SOC functions 0 Figure 25 5 Sampled Filtered 4B sa...

Page 627: ...is limited to Low Speed mode regardless of CR1 PMODE setting Windowed Sampled and Filtered modes are not supported The CMP output pin is latched and does not reflect the compare output state The posi...

Page 628: ...egister bit values They also apply to COUT for all sampling modes Filtering can be performed using an internal timebase defined by FPR FILT_PER to determine sample time The need for digital filtering...

Page 629: ...TER_CNT must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions The probability of detecting an actual output change within the nominal laten...

Page 630: ...IEF or both the corresponding change on COUT forces a DMA transfer request rather than a CPU interrupt instead When the DMA has completed the transfer it sends a transfer completing indicator that dea...

Page 631: ...ntains a 64 tap resistor ladder network and a 64 to 1 multiplexer which selects an output voltage from one of 64 distinct levels that outputs from DACO It is controlled through the DAC Control Registe...

Page 632: ...DAC are configured to CMP Trigger mode when CMP_CR1 TRIGM is set to 1 In addition the CMP must be enabled If the DAC is to be used as a reference to the CMP it must also be enabled CMP Trigger mode d...

Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...

Page 634: ...the analog comparator op amps or ADC 26 2 Features The features of the DAC module include On chip programmable reference generator output The voltage output range is from 1 4096 Vin to Vin and the ste...

Page 635: ...PBF DACBBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 26 1 DAC block diagram 26 4 Memory map register definition The DAC has registers to control analog comparator and...

Page 636: ...ress 4003_F000h base 0h offset 2d i where i 0d to 1d Bit 7 6 5 4 3 2 1 0 Read DATA0 Write Reset 0 0 0 0 0 0 0 0 DACx_DATnL field descriptions Field Description DATA0 DATA0 When the DAC buffer is not e...

Page 637: ...32 16 bit accesses to this register Address 4003_F000h base 20h offset 4003_F020h Bit 7 6 5 4 3 2 1 0 Read 0 0 DACBFRPT F DACBFRPB F Write Reset 0 0 0 0 0 0 1 0 DACx_SR field descriptions Field Descri...

Page 638: ...ed 1 The DAC software trigger is selected 4 DACSWTRG DAC Software Trigger Active high This is a write only field which always reads 0 If DAC software trigger is selected and buffer is enabled writing...

Page 639: ...Enable Select 0 DMA is disabled 1 DMA is enabled When DMA is enabled the DMA request will be generated by original interrupts The interrupts will not be presented on this module at the same time 6 3...

Page 640: ...s DACREF_1 and DACREF_2 as the DAC reference voltage Vin by C0 DACRFS See the chip specific DAC information to determine the source options for DACREF_1 and DACREF_2 When the DAC is enabled it convert...

Page 641: ...ation Modes Description Buffer Normal mode This is the default mode The buffer works as a circular buffer The read pointer increases by one every time the trigger occurs When the read pointer reaches...

Page 642: ...e normally if enabled Stop mode If enabled the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop In low power stop modes the DAC is fully shut...

Page 643: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 512 Freescale Semiconductor Inc...

Page 644: ...1 TPM Philosophy The TPM is built upon a very simple timer HCS08 Timer PWM Module TPM used for many years on Freescale s 8 bit microcontrollers The TPM extends the functionality to support operation...

Page 645: ...y reset or cause the counter to start incrementing The counter can also optionally stop incrementing on counter overflow Support the generation of hardware triggers when the counter overflows and per...

Page 646: ...nnel N MSNB MSNA ELSNB ELSNA input capture mode logic channel N input CNV CHNIE CHNF channel N interrupt channel N output signal output modes logic generation of channel N outputs signals in output co...

Page 647: ...ssigned for that channel 27 3 Memory Map and Register Definition This section provides a detailed description of all TPM registers Attempting to access a reserved register location in the TPM memory m...

Page 648: ...523 4003_9024 Channel n Status and Control TPM1_C3SC 32 R W 0000_0000h 27 3 4 521 4003_9028 Channel n Value TPM1_C3V 32 R W 0000_0000h 27 3 5 523 4003_902C Channel n Status and Control TPM1_C4SC 32 R...

Page 649: ...tatus flag and control bits used to configure the interrupt enable module configuration and prescaler factor These controls relate to all channels within this module Address Base address 0h offset Bit...

Page 650: ...ne 5 CPWMS Center Aligned PWM Select Selects CPWM mode This mode configures the TPM to operate in up down counting mode This field is write protected It can be written only when the counter is disable...

Page 651: ...contains the modulo value for the TPM counter When the TPM counter reaches the modulo value and increments the overflow flag TOF is set and the next value of TPM counter depends on the selected count...

Page 652: ...l Selection CPWMS MSnB MSnA ELSnB ELSnA Mode Configuration X 00 00 None Channel disabled X 01 00 Software compare Pin not used for TPM 0 00 01 Input capture Capture on Rising Edge Only 10 Capture on F...

Page 653: ...operation has no effect therefore CHF remains set indicating another event has occurred In this case a CHF interrupt request is not lost due to the delay in clearing the previous CHF 0 No channel eve...

Page 654: ...modes In input capture mode any write to a CnV register is ignored In compare modes writing to a CnV register latches the value into a buffer A CnV register is updated with the value of its write buff...

Page 655: ...effect therefore CHF remains set indicating another event has occurred In this case a CHF interrupt request is not lost due to the clearing sequence for a previous CHF Address Base address 50h offset...

Page 656: ...occurred 1 A channel event has occurred 3 CH3F Channel 3 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 2 CH2F Channel 2 Flag See the register descrip...

Page 657: ...n set the TPM counter will reload with 0 and initialize PWM outputs to their default value when a rising edge is detected on the selected trigger input The trigger input is ignored if the TPM counter...

Page 658: ...res the TPM to use an externally generated global time base counter When an externally generated timebase is used the internal TPM counter is not used by the channels but can be used to generate a per...

Page 659: ...ther disable the TPM counter or select one of two possible clock modes for the TPM counter After any reset CMOD 1 0 0 0 so the TPM counter is disabled The CMOD 1 0 bits may be read or written at any t...

Page 660: ...by the channels either for input or output modes The counter updates from the selected clock divided by the prescaler The TPM counter has these modes of operation up counting see Up counting up down...

Page 661: ...3 2 Up down counting Up down counting is selected when SC CPWMS 1 When configured for up down counting configuring CONF MOD to less than 2 is not supported The value of 0 is loaded into the TPM count...

Page 662: ...ounter is not generating the global time base then it can be used as an independent counter or pulse accumulator 27 4 3 5 Counter trigger The TPM counter can be configured to start stop or reset in re...

Page 663: ...or the channel input signal to be detected correctly is counter clock divided by 4 which is required to meet Nyquist criteria for signal sampling Writes to the CnV register are ignored in input captur...

Page 664: ...t is set and the channel n interrupt is generated if CHnIE 1 at the channel n match TPM counter CnV TOF bit 0 1 1 1 2 2 3 3 4 4 5 5 0 0 previous value previous value channel n output counter overflow...

Page 665: ...MOD 0x0001 and the pulse width duty cycle is determined by CnV The CHnF bit is set and the channel n interrupt is generated if CHnIE 1 at the channel n match TPM counter CnV that is at the end of the...

Page 666: ...low 0 1 2 3 4 5 6 7 8 0 1 2 previous value Figure 27 11 EPWM signal with ELSnB ELSnA X 1 If CnV 0x0000 then the channel n output is a 0 duty cycle EPWM signal If CnV MOD then the channel n output is a...

Page 667: ...ELSnA 1 0 If ELSnB ELSnA 0 0 when the TPM counter reaches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not cont...

Page 668: ...gnal 27 4 8 Registers Updated from Write Buffers 27 4 8 1 MOD Register Update If CMOD 1 0 0 0 then MOD register is updated when MOD register is written If CMOD 1 0 0 0 then MOD register is updated acc...

Page 669: ...rrupt is not generated 0 1 The channel overflow DMA transfer request is not generated The channel overflow interrupt is generated if CHnF TOF 1 1 0 The channel overflow DMA transfer request is generat...

Page 670: ...et occurs When the TPM exits from reset the TPM counter and the prescaler counter are zero and are stopped CMOD 1 0 0 0 the timer overflow interrupt is zero the channels interrupts are zero the channe...

Page 671: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 540 Freescale Semiconductor Inc...

Page 672: ...odule s instances see the chip configuration information The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels 28 1 1 Block diagram The following figure sh...

Page 673: ...of PIT channels used in this MCU 28 1 2 Features The main features of this block are Ability of timers to generate DMA trigger pulses Ability of timers to generate interrupts Maskable interrupts Inde...

Page 674: ...egister PIT_CVAL0 32 R 0000_0000h 28 3 5 546 4003_7108 Timer Control Register PIT_TCTRL0 32 R W 0000_0000h 28 3 6 546 4003_710C Timer Flag Register PIT_TFLG0 32 R W 0000_0000h 28 3 7 547 4003_7110 Tim...

Page 675: ...ers is disabled 0 FRZ Freeze Allows the timers to be stopped when the device enters the Debug mode 0 Timers continue to run in Debug mode 1 Timers are stopped in Debug mode 28 3 2 PIT Upper Lifetime T...

Page 676: ...ing counter Access User read only Address 4003_7000h base E4h offset 4003_70E4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LTL W Reset 0 0 0 0 0 0 0 0...

Page 677: ...12 11 10 9 8 7 6 5 4 3 2 1 0 R TVL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_CVALn field descriptions Field Description TVL Current Timer Value Represents the curren...

Page 678: ...ests from Timer n are disabled 1 Interrupt will be requested whenever TIF is set 0 TEN Timer Enable Enables or disables the timer 0 Timer n is disabled 1 Timer n is enabled 28 3 7 Timer Flag Register...

Page 679: ...ailable on a separate interrupt line 28 4 1 1 Timers The timers generate triggers at periodic intervals when enabled The timers load the start values as specified in their LDVAL registers count down t...

Page 680: ...er period without restarting the timer by writing LDVAL with the new load value This value will then be loaded after the next trigger event See the following figure Timer enabled p1 p1 Start value p1...

Page 681: ...clock has a frequency of 50 MHz Timer 1 creates an interrupt every 5 12 ms Timer 3 creates a trigger event every 30 ms The PIT module must be activated by writing a 0 to MCR MDIS The 50 MHz clock freq...

Page 682: ...is set up to trigger every 6 s 600 million cycles Timer 2 is chained to Timer 1 and programmed to trigger 10 times The value for the LDVAL register trigger is calculated as number of cycles 1 so LDVAL...

Page 683: ...following example code matches the described setup turn on PIT PIT_MCR 0x00 Timer 1 PIT_LDVAL1 0xFFFFFFFF setup timer 1 for maximum counting period PIT_TCTRL1 0x0 disable timer 1 interrupts PIT_TCTRL1...

Page 684: ...events allowing it to be used as a time of day counter 29 1 1 Features The features of the LPTMR module include 16 bit time counter or pulse counter with compare Optional interrupt can generate asynch...

Page 685: ...Table 29 2 LPTMR signal descriptions Signal I O Description LPTMR0_ALTn I Pulse Counter Input pin 29 2 1 Detailed signal descriptions Table 29 3 LPTMR interface detailed signal descriptions Signal I...

Page 686: ...ld Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 TCF Timer Compare Flag TCF is set when the LPTMR is enabled and the CNR equals the CMR...

Page 687: ...abled 0 CNR is reset whenever TCF is set 1 CNR is reset on overflow 1 TMS Timer Mode Select Configures the mode of the LPTMR TMS must be altered only when the LPTMR is disabled 0 Time Counter mode 1 P...

Page 688: ...ler clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges 1010 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 r...

Page 689: ...R equals the value in the CMR and increments TCF is set and the hardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger will remain asserted until the LPTM...

Page 690: ...PTMR counter is reset to zero following a warm reset 29 4 2 LPTMR clocking The LPTMR prescaler glitch filter can be clocked by one of the four clocks The clock source must be enabled before the LPTMR...

Page 691: ...every clock cycle When the LPTMR is enabled the first increment will take an additional one or two prescaler clock cycles due to synchronization logic 29 4 3 3 Glitch filter In Pulse Counter mode when...

Page 692: ...generated CNR is reset if CSR TFC is clear When the LPTMR is enabled the CMR can be altered only when CSR TCF is set When updating the CMR the CMR must be written and CSR TCF must be cleared before th...

Page 693: ...re trigger is always enabled When Then The CMR is set to 0 with CSR TFC clear The LPTMR hardware trigger will assert on the first compare and does not deassert The CMR is set to a nonzero value or if...

Page 694: ...n and 32 bit alarm 16 bit prescaler with compensation that can correct errors between 0 12 ppm and 3906 ppm Register write protection Lock register requires POR or software reset to enable write acces...

Page 695: ...register protected by the lock register does not generate a bus error but the write will not complete RTC memory map Absolute address hex Register name Width in bits Access Reset value Section page 40...

Page 696: ...R will read as zero when SR TIF or SR TOF are set indicating the time is invalid 30 2 2 RTC Time Prescaler Register RTC_TPR Address 4003_D000h base 4h offset 4003_D004h Bit 31 30 29 28 27 26 25 24 23...

Page 697: ...the CIR If the CIC does not equal zero then it is decremented once a second 23 16 TCV Time Compensation Value Current value used by the compensation logic for the present second interval Updated once...

Page 698: ...egister RTC_CR Address 4003_D000h base 10h offset 4003_D010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 699: ...e time counter to allow the 32 768 kHz clock time to stabilize 7 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 WPS Wakeup Pin Select The wakeup pin is...

Page 700: ...TOF TIF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RTC_SR field descriptions Field Description 31 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 TCE Time...

Page 701: ...ero 30 2 7 RTC Lock Register RTC_LR Address 4003_D000h base 18h offset 4003_D018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10...

Page 702: ...s the value 1 30 2 8 RTC Interrupt Enable Register RTC_IER Address 4003_D000h base 1Ch offset 4003_D01Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 703: ...ag does generate an interrupt 1 TOIE Time Overflow Interrupt Enable 0 Time overflow flag does not generate an interrupt 1 Time overflow flag does generate an interrupt 0 TIIE Time Invalid Interrupt En...

Page 704: ...ements once every second and a 16 bit prescaler register that increments once every 32 768 kHz clock cycle Reading the time counter either seconds or prescaler while it is incrementing may return inva...

Page 705: ...firmware that periodically measures the external temperature via ADC and updates the compensation register based on a look up table that specifies the change in crystal frequency over temperature The...

Page 706: ...IF or SR TOF are set This allows the time seconds and prescaler registers to be initialized whenever time is invalidated while preventing the time seconds and prescaler registers from being changed on...

Page 707: ...here is no corresponding status flag to clear It is enabled in the RTC by the time seconds interrupt enable bit and enabled at the chip level by setting the chip specific RTC clock gate control bit Th...

Page 708: ...he SPI module clock divided by four in slave mode Software can poll the status flags or SPI operation can be interrupt driven NOTE For the actual maximum SPI baud rate refer to the Chip Configuration...

Page 709: ...peration The SPI functions in the following three modes Run mode This is the basic mode of operation Wait mode SPI operation in Wait mode is a configurable low power mode controlled by the SPISWAI bit...

Page 710: ...wing SPI system connections the internal organization of the SPI module and the SPI clock dividers that control the master mode bit rate 31 1 3 1 SPI system block diagram The following figure shows th...

Page 711: ...an 8 byte transmit FIFO that once enabled provide features to allow fewer CPU interrupts to occur when transmitting receiving high volume high speed data When FIFO mode is enabled the SPI can still f...

Page 712: ...N SSOE SPC0 BIDIROE IN FIFOMODE Rx FIFO 64 bits deep Tx BUFFER EMPTY Rx BUFFER FULL SHIFT CLOCK Tx FIFO 64 bits deep 8 OR 16 BIT MODE SPIMODE RNFULLF RNFULLIEN TNEAREF TNEARIEN MH ML RX BUFFER NOT EMP...

Page 713: ...zero SPC0 is 0 not bidirectional mode this pin is the serial data input When the SPI is enabled as a slave and SPC0 is 0 this pin is the serial data output If SPC0 is 1 to select single wire bidirecti...

Page 714: ...PI0_C3 8 R W 00h 31 3 10 595 4007_7000 SPI Status Register SPI1_S 8 R 20h 31 3 1 583 4007_7001 SPI Baud Rate Register SPI1_BR 8 R W 00h 31 3 2 587 4007_7002 SPI Control Register 2 SPI1_C2 8 R W 00h 31...

Page 715: ...DF RNFULLF TNEAREF TXFULLF RFIFOEF Write w1c Reset 0 0 1 0 0 0 0 0 SPIx_S field descriptions Field Description 7 SPRF SPI Read Buffer Full Flag when FIFO is not supported or not enabled or SPI read FI...

Page 716: ...the transmit buffer If no new data is waiting in the transmit buffer SPTEF simply remains set and no data moves from the buffer to the shifter When the FIFO is supported and enabled FIFOMODE is 1 This...

Page 717: ...TNEAREF_MARK is 1 remaining to transmit 1 Transmit FIFO has an amount of data equal to or less than 16 bits when C3 TNEAREF_MARK is 0 or 32 bits when C3 TNEAREF_MARK is 1 remaining to transmit 1 TXFU...

Page 718: ...aud rate prescaler divisor is 1 001 Baud rate prescaler divisor is 2 010 Baud rate prescaler divisor is 3 011 Baud rate prescaler divisor is 4 100 Baud rate prescaler divisor is 5 101 Baud rate presca...

Page 719: ...et and the interrupt from SPTEF is disabled 0 DMA request for transmit is disabled and interrupt from SPTEF is allowed 1 DMA request for transmit is enabled and interrupt from SPTEF is disabled 4 MODF...

Page 720: ...1 SPI configured for single wire bidirectional operation pin mode is bidirectional In master mode of operation MISO is not used by SPI MOSI is master in when BIDIROE is 0 or master I O when BIDIROE i...

Page 721: ...errupts from SPTEF inhibited use polling 1 When SPTEF is 1 hardware interrupt requested 4 MSTR Master Slave Mode Select Selects master or slave mode operation 0 SPI module configured as a slave SPI de...

Page 722: ...ter low SPIx_ML This register together with the MH register contains the hardware compare value When the value received in the SPI receive data buffer equals this hardware compare value the SPI Match...

Page 723: ...writing to the SPI data registers otherwise the write is ignored When the transmit DMA request is enabled TXDMAE is 1 when S SPTEF is set the SPI data registers can be written automatically by DMA wit...

Page 724: ...0 0 0 0 SPIx_DH field descriptions Field Description Bits 15 8 Data high byte 31 3 9 SPI clear interrupt register SPIx_CI This register applies only for an instance of the SPI module that supports the...

Page 725: ...more than 64 bits of data 0 No receive FIFO error occurred 1 A receive FIFO error occurred 5 TXFOF Transmit FIFO overflow flag This flag indicates that a transmit FIFO overflow condition has occurred...

Page 726: ...IFO is not full S TXFULLF is 0 As a result If C2 TXDMAE is 1 TXFULLF_b generates a transmit DMA request The DMA request remains active until TXFULLF is set to 1 indicating the transmit FIFO is full If...

Page 727: ...ored and has no function if the FIFOMODE bit is 0 0 No interrupt upon TNEAREF being set 1 Enable interrupts upon TNEAREF being set 1 RNFULLIEN Receive FIFO nearly full interrupt enable Writing 1 to th...

Page 728: ...o operate as a master or as a slave When the MSTR bit in SPI Control Register 1 is set master mode is selected when C1 MSTR is clear slave mode is selected 31 4 2 Master mode The SPI operates in maste...

Page 729: ...t error also sets the Mode Fault MODF flag in the SPI Status Register SPIx_S If the SPI Interrupt Enable bit SPIE is set when S MODF gets set then an SPI interrupt sequence is also requested When a wr...

Page 730: ...ystem slave s serial data output line As long as no more than one slave device drives the system slave s serial data output line it is possible for several slaves to receive the same transmission from...

Page 731: ...ss and must be avoided 31 4 4 SPI FIFO Mode When the FIFO feature is supported The SPI works in FIFO mode when the C3 FIFOMODE bit is set When the module is in FIFO mode the SPI RX buffer and SPI TX b...

Page 732: ...f SPI transmission by DMA is as below Configure SPI before Transmission RESET Configure DMA Controller for SPI Transmission Set TXDMAE RXDMAE 1 to enable Transmit Receive by DMA Set SPE 1 to start tra...

Page 733: ...the DMA controller to transfer data from memory to the SPI data register The DMA performs a single data transfer per DMA request in cycle steal mode Therefore a single byte word is written to the SPI...

Page 734: ...PIx_DH and SPIx_MH will be ignored In 16 bit mode SPIMODE 1 the SPI Data Register is comprised of two bytes SPIx_DH and SPIx_DL Reading either byte SPIx_DH or SPIx_DL latches the contents of both byte...

Page 735: ...bit 1 starting at the first SPSCK edge and bit 8 ending one half SPSCK cycle after the eighth SPSCK edge The MSB first and LSB first lines show the order of SPI data bits depending on the setting in...

Page 736: ...their MISO and MOSI inputs respectively At the third SPSCK edge the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the...

Page 737: ...ut of a master The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave The SS OUT waveform applies to the slave select output from...

Page 738: ...5 6 7 or 8 The rate select bits SPR3 SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 256 or 512 to get the internal SPI master mode bit rate clock The baud rate generato...

Page 739: ...his mode the SPI uses only one serial data pin for the interface with one or more external devices C1 MSTR decides which pin to use The MOSI pin becomes the serial data I O MOMI pin for the master mod...

Page 740: ...ts the MODF bit in the SPI status register automatically provided that C2 MODFEN is set In the special case where the SPI is in master mode and C2 MODFEN is cleared the SS pin is not used by the SPI I...

Page 741: ...ule enters a power conservation state when the CPU is in wait mode If C2 SPISWAI is set and the SPI is configured for master any transmission and reception in progress stops at Wait mode entry The tra...

Page 742: ...ype of stop mode the SPI module clock is disabled held high or low If the SPI is in master mode and exchanging data when the CPU enters the Stop mode the transmission is frozen until the CPU exits sto...

Page 743: ...terrupt service routine ISR should check the flag bits to determine which event caused the interrupt The service routine should also clear the flag bit s before returning from the ISR usually near the...

Page 744: ...en the data in the receive data buffer is equal to the data in the SPI Match Register In 8 bit mode SPMF is set only after bits 7 0 in the receive data buffer are determined to be equivalent to the va...

Page 745: ...the peripheral bus clock is stopped but internal logic states are retained 3 The SPI module is in slave mode 4 The received transmission ends 5 When the FIFO feature is supported FIFO mode is disable...

Page 746: ...is set up for master mode with only hardware match interrupts enabled The SPI runs in 16 bit mode at a maximum baud rate of SPI module clock divided by 2 Clock phase and polarity are set for an active...

Page 747: ...et when transmit data buffer is empty Bit 4 MODF 0 Mode fault flag for master mode Bit 3 0 0 FIFOMODE is not enabled SPIx_MH 0xXX In 16 bit mode this register holds bits 8 15 of the hardware match buf...

Page 748: ...F 1 SPTEF 1 INITIALIZE SPI SPIxC1 0x54 SPIxC2 SPIxBR 0x00 0xC0 SPIxMH 0xXX SPIxDH SPIxDL SPIxDH SPIxDL Figure 31 9 Initialization Flowchart Example for SPI Master Device in 16 bit Mode for FIFOMODE 0...

Page 749: ...FIFOMODE TXFULLF 1 RNFULLF 1 SPRF 1 RFIFOEF 1 SPIxDH SPIxDL SPIxDH SPIxDL SPIxMH 0xXX Figure 31 10 Initialization Flowchart Example for SPI Master Device in 16 bit Mode for FIFOMODE 1 Initialization a...

Page 750: ...d rate oversampling ratio from 4x to 32x Interrupt DMA or polled operation Transmit data register empty and transmission complete Receive data register full Receive overrun parity error framing error...

Page 751: ...p from Stop mode 32 1 2 2 Wait mode The UART can be configured to Stop in Wait modes when the DOZEEN bit is set The transmitter and receiver will finish transmitting receiving the current word 32 1 2...

Page 752: ...st LOOPS Load From UARTx_D TXINV BRK13 ASYNCH MODULE CLOCK BAUD Divider OSR Divider To TxD Pin TXDIR T8 SBK TE TCIE PE PT TDRE TC TIE RSRC M Pin Logic TO TxD TxD Direction Break All 0s Preamble All 1s...

Page 753: ...will generate a bus error UART memory map Absolute address hex Register name Width in bits Access Reset value Section page 4006_A000 UART Baud Rate Register High UART0_BDH 8 R W 00h 32 2 1 623 4006_A0...

Page 754: ...eld descriptions Field Description 7 LBKDIE LIN Break Detect Interrupt Enable for LBKDIF 0 Hardware interrupts from UART_S2 LBKDIF disabled use polling 1 Hardware interrupt requested when UART_S2 LBKD...

Page 755: ...R 12 0 are referred to collectively as BR They set the modulo divide rate for the baud rate generator When BR is 1 8191 the baud rate equals baud clock OSR 1 BR 32 2 3 UART Control Register 1 UARTx_C1...

Page 756: ...Receiver and transmitter use 9 bit data characters 3 WAKE Receiver Wakeup Method Select 0 Idle line wakeup 1 Address mark wakeup 2 ILT Idle Line Type Select Setting this bit to 1 ensures that the sto...

Page 757: ...1 3 TE Transmitter Enable TE must be 1 to use the UART transmitter When TE is set the UART forces the UART_TX pin to act as an output for the UART system When the UART is configured for single wire op...

Page 758: ...0 Normal transmitter operation 1 Queue break character s to be sent 32 2 5 UART Status Register 1 UARTx_S1 Address Base address 4h offset Bit 7 6 5 4 3 2 1 0 Read TDRE TC RDRF IDLE OR NF FE PF Write...

Page 759: ...lag OR is set when a new serial character is ready to be transferred to the receive data buffer but the previously received character has not been read from UART_D yet In this case the new character a...

Page 760: ..._S2 field descriptions Field Description 7 LBKDIF LIN Break Detect Interrupt Flag LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected LBKDIF is cleared b...

Page 761: ...smitted break character length Detection of a framing error is not affected by the state of this bit This bit should only be changed when the transmitter is disabled 0 Break character is transmitted w...

Page 762: ...fer after UART_D is written so T8 should be written if it needs to change from its previous value before UART_D is written If T8 does not need to change in the new value such as when it is used to gen...

Page 763: ...use polling 1 Hardware interrupt requested when PF is set 32 2 8 UART Data Register UARTx_D This register is actually two separate registers Reads return the contents of the read only receive data buf...

Page 764: ...The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4 MAEN bit is set If a match occurs the following data is transferred to the da...

Page 765: ...ode Enable 1 Refer to Match address operation for more information 0 All data received is transferred to the data buffer if MAEN2 is cleared 1 All data received with the most significant bit cleared i...

Page 766: ...itter DMA Enable TDMAE configures the transmit data register empty flag S1 TDRE to generate a DMA request 0 DMA request disabled 1 DMA request enabled 6 Reserved This field is reserved This read only...

Page 767: ...e following describes each of the blocks of the UART 32 3 1 Baud rate generation A 13 bit modulus counter in the baud rate generator derive the baud rate for both the receiver and the transmitter The...

Page 768: ...the transmit shift register is available for a new UART character the value waiting in the transmit data register is transferred to the shift register synchronized with the baud rate clock and the tra...

Page 769: ...the shifter is available As long as the character in the shifter does not finish whileUART_C2 TE is cleared the UART transmitter never actually releases control of the UART_TX pin The length of the b...

Page 770: ...ts an oversampling rate of between 4 and 32 of the baud rate clock for sampling The receiver starts by taking logic level samples at the oversampling rate times the baud rate to search for a falling e...

Page 771: ...each message and as soon as they determine the message is intended for a different receiver they write logic 1 to the receiver wake up control bit UART_C2 RWU When RWU bit is set the status flags asso...

Page 772: ...F flag In this case the character with the msb set is received even though the receiver was sleeping during most of this character time 32 3 3 2 3 Match address operation Match address operation is en...

Page 773: ...eiver these bits are held in UART_C3 R8 and UART_C3 R9 For coherent writes to the transmit data buffer write to UART_C3 T8 and UART_C3 T9 before writing to UART_D If the bit values to be transmitted a...

Page 774: ...ut driven by the transmitter the internal loop back connection is disabled and as a result the receiver cannot receive characters that are sent out by the transmitter 32 3 5 Interrupts and status flag...

Page 775: ...nded period of time IDLE is cleared by writing 1 to the UART_S1 IDLE flag After UART_S1 IDLE has been cleared it cannot become set again until the receiver has received at least one new character and...

Page 776: ...transmission complete Receive data register full Receive overrun parity error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity...

Page 777: ...MSB UART DATA REGISTER UART_D LOAD FROM UART_D TRANSMITTER CONTROL M INTERNAL BUS SBR12 SBR0 16 MODULE CLOCK LOOP RSRC TE TO CONTROL RECEIVER LOOPS TXINV TXDIR TxD SHIFT DIRECTION TXINV DMA done TDRE...

Page 778: ...L FROM TRANSMITTER ACTIVE EDGE DETECT LBKDE RIE IDLE ILIE LBKDIF LBKDIE OR ORIE FE FEIE NF NEIE PF PEIE RWUID Rx Interrupt DMA Request From RxD Pin ipp_ind_sci_rx UART DATA REGISTER UART_D BAUD DIVIDE...

Page 779: ...g Whether TxD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings Timing Driven at the beginning or within a bit time according to the bit encoding me...

Page 780: ...rol Register 2 UART2_C2 8 R W 00h 33 3 4 652 4006_C004 UART Status Register 1 UART2_S1 8 R C0h 33 3 5 654 4006_C005 UART Status Register 2 UART2_S2 8 R W 00h 33 3 6 655 4006_C006 UART Control Register...

Page 781: ...his register along with UART_BDH control the prescale divisor for UART baud rate generation To update the 13 bit baud rate setting SBR12 SBR0 first write to UART_BDH to buffer the high half of the new...

Page 782: ...RSRC Receiver Source Select This field has no meaning or effect unless LOOPS is set to 1 When LOOPS is set the receiver input is internally connected to the TxD pin and RSRC determines whether this co...

Page 783: ...n parity means the total number of 1s in the data character including the parity bit is even 0 Even parity 1 Odd parity 33 3 4 UART Control Register 2 UARTx_C2 This register can be read or written at...

Page 784: ...en if RE is set 0 Receiver off 1 Receiver on 1 RWU Receiver Wakeup Control A 1 can be written to this field to place the UART receiver in a standby state where it waits for automatic hardware detectio...

Page 785: ...1 Queue a break character by writing 1 to UART_C2 SBK 0 Transmitter active sending data a preamble or a break 1 Transmitter idle transmission activity complete 5 RDRF Receive Data Register Full Flag R...

Page 786: ...To clear NF read UART_S1 and then read the UART data register UART_D 0 No noise detected 1 Noise detected in the received character in UART_D 1 FE Framing Error Flag FE is set at the same time as RDRF...

Page 787: ...ved This read only field is reserved and always has the value 0 4 RXINV Receive Data Inversion Setting this field reverses the polarity of the received data input NOTE Setting RXINV inverts the RxD in...

Page 788: ...nfigured for 9 bit data C1 M 1 R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the UART_D register When reading 9 bit data read R8 before reading UART_D...

Page 789: ...sted when NF is set 1 FEIE Framing Error Interrupt Enable Enables the framing error flag FE to generate hardware interrupt requests 0 FE interrupts disabled use polling 1 Hardware interrupt requested...

Page 790: ...TDMAS Transmitter DMA Select TDMAS configures the transmit data register empty flag TDRE to generate interrupt or DMA requests if TIE is set NOTE If UART_C2 TIE is cleared TDRE DMA and TDRE interrupt...

Page 791: ...always has the value 0 33 4 Functional description The UART allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The UART comprises a baud ra...

Page 792: ...mitter is enabled by setting the TE bit in UART_C2 This queues a preamble character that is one full character frame of the idle state The transmitter then remains idle until data is available in the...

Page 793: ..._S1 FE 1 occurs When idle line wake up is used a full character time of idle logic 1 is needed between messages to wake up any sleeping receivers Normally a program would wait for UART_S1 TDRE to beco...

Page 794: ...t indicating the receive data register buffer was already full the overrun OR status flag is set and the new data is lost Because the UART receiver is double buffered the program has one full characte...

Page 795: ...dges anywhere in the character frame In the case of a framing error provided the received character was not a break character the sampling logic that searches for a falling edge is filled with three l...

Page 796: ...of a character count toward the full character time of idle When UART_C1 ILT is set the idle bit counter does not start until after a stop bit time so the idle detection is not affected by the data in...

Page 797: ...IE local interrupt masks are cleared When a program detects that the receive data register is full UART_S1 RDRF 1 it gets the data from the receive data register by reading UART_D The UART_S1 RDRF fla...

Page 798: ...transmitter bit times and receiver bit times 33 4 5 1 Slow data tolerance Figure 33 4 shows how much a slow received frame can be misaligned without causing a noise error or a framing error The slow s...

Page 799: ...fference between the receiver count and the transmitter count of a slow 9 bit and 2 stop bits character with no errors is 186 179 186 X 100 3 76 33 4 5 2 Fast data tolerance Figure 33 5 shows how much...

Page 800: ...transmitter count of a fast 9 bit and 2 stop bits character with no errors is 186 192 186 x 100 3 23 33 4 6 DMA Operation In the transmitter flags TDRE and TC can be configured to assert a DMA transf...

Page 801: ...ninth bit of a new character is the same as for the previous character it is not necessary to write to UART_C3 T8 again When data is transferred from the transmit data buffer to the transmit shifter...

Page 802: ...ingle wire operation When UART_C1 LOOPS is set UART_C1 RSRC chooses between loop mode UART_C1 RSRC 0 or single wire mode UART_C1 RSRC 1 Single wire mode implements a half duplex serial connection The...

Page 803: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 672 Freescale Semiconductor Inc...

Page 804: ...n The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function provided the corresponding Port Control and Interrupt module for that pin is ena...

Page 805: ...input output I O PORTE31 PORTE0 General purpose input output I O NOTE Not all pins within each port are implemented on each device See the chapter on signal multiplexing for the number of GPIO ports a...

Page 806: ...number of pins per port and therefore the number of usable control bits per port register is chip specific Refer to the Chip Configuration chapter to see the exact control bits for the non identical...

Page 807: ...00F_F08C Port Toggle Output Register GPIOC_PTOR 32 W always reads 0 0000_0000h 34 2 4 678 400F_F090 Port Data Input Register GPIOC_PDIR 32 R 0000_0000h 34 2 5 679 400F_F094 Port Data Direction Registe...

Page 808: ...ss 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PDO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDOR field de...

Page 809: ...ns Field Description PTCO Port Clear Output Writing to this register will update the contents of the corresponding bit in the Port Data Output Register PDOR as follows 0 Corresponding bit in PDORn doe...

Page 810: ...0 0 GPIOx_PDIR field descriptions Field Description PDI Port Data Input Reads 0 at the unimplemented pins for a particular device Pins that are not configured for a digital function read 0 If the Por...

Page 811: ...which complete with one wait state NOTE For simplicity each FGPIO port s registers appear with the same width of 32 bits corresponding to 32 pins The actual number of pins per port and therefore the...

Page 812: ...Clear Output Register FGPIOC_PCOR 32 W always reads 0 0000_0000h 34 3 3 683 F800_008C Port Toggle Output Register FGPIOC_PTOR 32 W always reads 0 0000_0000h 34 3 4 683 F800_0090 Port Data Input Regist...

Page 813: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PDO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PDOR field descriptions Field Description PDO Port Data Output Un...

Page 814: ...ield Description PTCO Port Clear Output Writing to this register will update the contents of the corresponding bit in the Port Data Output Register PDOR as follows 0 Corresponding bit in PDORn does no...

Page 815: ...disabled then the corresponding bit in PDIR does not update 0 Pin logic level is logic 0 or is not configured for use by digital function 1 Pin logic level is logic 1 34 3 6 Port Data Direction Regist...

Page 816: ...tate of the pin is equal to the corresponding port data output register To facilitate efficient bit manipulation on the general purpose outputs pin data set pin data clear and pin data toggle register...

Page 817: ...ace only Since the clocks to the Port Control and Interrupt modules are disabled during Compute Operation the Pin Data Input Registers do not update with the current state of the pins Functional descr...

Page 818: ...the conversion result is out of the range specified by TSI threshold It provides a solid capacitive measurement module to the implementation of touch keyboard rotaries and sliders 35 1 1 Features TSI...

Page 819: ...his mode When a scan completes TSI submits an interrupt request to CPU if the interrupt is enabled Run TSI module is fully functional in this mode When a scan completes TSI submits an interrupt reques...

Page 820: ...st be kept as short as possible to reduce distribution capacity on board 35 3 Register definition This section describes the memory map and control status registers for the TSI module TSI memory map A...

Page 821: ...UTRGF Out of Range Flag This flag is set if the result register of the enabled electrode is out of the range defined by the TSI_THRESHOLD register This flag is set only when TSI is configured in non n...

Page 822: ...100 Set TSI analog to work in automatic noise detection mode 23 21 REFCHRG REFCHRG These bits indicate the reference oscillator charge and discharge current value 000 500 nA 001 1 A 010 2 A 011 4 A 10...

Page 823: ...ectrode 00110 7 times per electrode 00111 8 times per electrode 01000 9 times per electrode 01001 10 times per electrode 01010 11 times per electrode 01011 12 times per electrode 01100 13 times per el...

Page 824: ...rogress 0 Software trigger scan 1 Hardware trigger scan 3 SCNIP Scan In Progress Status This read only bit indicates if scan is in progress This bit will get asserted after the analog bias circuit is...

Page 825: ...nt channel to be measured In hardware trigger mode TSI_GENCS STM 1 the scan will not start until the hardware trigger occurs In software trigger mode TSI_GENCS STM 0 the scan starts immediately when T...

Page 826: ...effect 1 Start a scan to determine which channel is specified by TSI_DATA TSICH 21 16 Reserved This field is reserved This read only field is reserved and always has the value 0 TSICNT TSI Conversion...

Page 827: ...n the following figure A configurable constant current source is used to charge and discharge the external electrode capacitance A buffer hysteresis defines the oscillator delta voltage The delta volt...

Page 828: ...rode oscillator frequency The current source is used to accommodate the TSI electrode oscillator frequency with different electrode capacitance sizes 35 4 1 2 Electrode oscillator and counter module c...

Page 829: ...SI electrode oscillator The TSI reference oscillator instead of using an external capacitor for the electrode oscillator has an internal reference capacitor The TSI reference oscillator has an indepen...

Page 830: ...ware trigger The TSI module allows a software or hardware trigger to start a scan When a software trigger is applied TSI_GENCS STM bit clear the TSI_GENCS SWTS bit must be written 1 to start the scan...

Page 831: ...Reference voltage The TSI module offers a internal reference voltage for both electrode oscillator and reference oscillator The internal reference voltage can work in low power modes even when the MC...

Page 832: ...soon as scan completes a DMA transfer request is asserted to DMA controller for data movement generally DMA engine will fetch TSI conversion result from TSI_DATA register store it to other memory spac...

Page 833: ...ion mode is used to detect power of noise In this mode the thresholds are incremented internally by TSI until the point that there is no noise voltage trepassing the threshold The noise detection mode...

Page 834: ...CNTH TSI_CNTL clk_ext clk_ref Cref Cap Mode REFCHRG EXTCHRG DVOLT 1pF PS NSCN prescaler counter2 clk en clk_ext clk_ref Cref REFCHRG EXTCHRG DVOLT 1pF PS NSCN Filter Filter STAT 1 0 STAT 1 0 Noise Mod...

Page 835: ...black points can be used The valid Rs Dvolt values are 184K 0 29V 77K 0 29V 77K 0 43V 32K 0 43V 32K 0 73V 14K 0 73V 14K 1 03V 5K 1 03V To determine the noise level the TSI noise detection algorithm sh...

Page 836: ...o the max value by writing 011b to TSI_CS2 EXTCHRG and DVOLT to the minimum value by writing 11b to TSI_CS2 DVOLT b Set up TSI_CS2 REFCHRG TSI_CS1 PS and TSI_CS1 NSCN bits to set the noise detection m...

Page 837: ...1 if Rs maximum value i e TSI_CS2 EXTCHRG 011b Now a matching DVOLT corresponding to the noise level is found 14 END NOTE The END condition of above algorithm can be one of TSI counter value within t...

Page 838: ...bserve in the following figure that in noise detection mode the clkref output has the peak detection and the number of detected peaks can be counted or used by digital block The clkext output has the...

Page 839: ...the module until the point that there is no noise voltage trepassing the threshold The following diagram shows how it is done The threshold comparator output goes to a counter and as the DVOLT control...

Page 840: ...operation with frequency limitation and automatic threshold counter I 00 EXTCHRG 2 1 In this operation mode these bits select the number of filter bits 00 3 filter bits 01 2 filter bits 10 1 filter b...

Page 841: ...LT 1 0 EXTCHRG 2 1 In this operation mode these 4 bits are used select the noise threshold These combinations are the maximum possible combinations however in real application only the valid combinati...

Page 842: ...0 V 1111 DVpm 1 630 V Vp 1 630 V Vm 0 V EXTCHRG 0 In this operation mode this bits selects the series resistance 0 uses Rs 32 k 1 uses Rs 187 k Independent of this bit selection the threshold 15 is d...

Page 843: ...Functional description MKW01Z128 MCU Reference Manual Rev 3 04 2016 712 Freescale Semiconductor Inc...

Page 844: ...ing at higher baud rates up to a maximum of clock 20 with reduced bus loading The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance...

Page 845: ...on The I2C module s operation in various low power modes is as follows Run mode This is the basic mode of operation To conserve power in this mode disable the module Wait mode The module continues to...

Page 846: ...gure 36 1 I2C Functional block diagram 36 2 I2C signal descriptions The signal properties of I2C are shown in the table found here Table 36 1 I2C signal descriptions Signal Description I O SCL Bidirec...

Page 847: ...4006_600A I2C SCL Low Timeout Register High I2C0_SLTH 8 R W 00h 36 3 11 727 4006_600B I2C SCL Low Timeout Register Low I2C0_SLTL 8 R W 00h 36 3 12 728 4006_7000 I2C Address Register 1 I2C1_A1 8 R W 00...

Page 848: ...2 1 0 Read MULT ICR Write Reset 0 0 0 0 0 0 0 0 I2Cx_F field descriptions Field Description 7 6 MULT Multiplier Factor Defines the multiplier factor mul This factor is used along with the SCL divider...

Page 849: ...ue For example if the I2C module clock speed is 8 MHz the following table shows the possible hold time values with different ICR and MULT selections to achieve an I2C baud rate of 100 kbit s MULT ICR...

Page 850: ...if FACK is cleared or the current receiving byte if FACK is set 1 No acknowledge signal is sent to the bus on the following receiving data byte if FACK is cleared or the current receiving data byte if...

Page 851: ...data register in transmit mode 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed As A Slave This bit is set by one of the following conditions The calling address matches the programmed pri...

Page 852: ...software by writing 1 to it such as in the interrupt routine One of the following events can set this bit One byte transfer including ACK NACK bit completes if FACK is 0 An ACK or NACK is sent on the...

Page 853: ...Data register does not initiate the receive Reading the Data register returns the last byte received while the I2C module is configured in master receive or slave receive mode The Data register does...

Page 854: ...isters When this bit is set a slave address matching occurs for any address greater than the value of the A1 register and less than or equal to the value of the RA register 0 Range mode disabled No ad...

Page 855: ...ystem software will receive the interrupt triggered by the I2C Status Register s TCF bit after the MCU wakes from the stop mode 0 Stop holdoff is disabled The MCU s entry to stop mode is not gated 1 S...

Page 856: ...trol and Status register I2Cx_SMB NOTE When the SCL and SDA signals are held high for a length of time greater than the high timeout period the SHTF1 flag sets Before reaching this threshold while the...

Page 857: ...r Clock Select Selects the clock source of the timeout counter 0 Timeout counter counts at the frequency of the I2C module clock 64 1 Timeout counter counts at the frequency of the I2C module clock 3...

Page 858: ...ess used by the SMBus This field is used on the device default address or other related addresses 0 Reserved This field is reserved This read only field is reserved and always has the value 0 36 3 11...

Page 859: ...a serial data line SDA and a serial clock line SCL for data transfers All devices connected to it must have open drain or open collector outputs A logic AND function is exercised on both lines with e...

Page 860: ...igh to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer might contain several bytes of data and brings all slaves out of their idle s...

Page 861: ...is signaled from the receiving device by pulling SDA low at the ninth clock In summary one complete data transfer needs nine clock pulses If the slave receiver does not acknowledge the master in the n...

Page 862: ...case the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets a status bit to indicate the loss of arbitration 36 4 1 7 Clock synchronization Because wire AN...

Page 863: ...w a slave can drive SCL low for the required period and then release it If the slave s SCL low period is greater than the master s SCL low period the resulting SCL bus signal s low period is stretched...

Page 864: ...97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 12...

Page 865: ...7 bits 11110 AD10 AD9 R W 0 A1 Slave address second byte AD 8 1 A2 Data A Data A A P After the master transmitter has sent the first byte of the 10 bit address the slave receiver sees an I2C interrup...

Page 866: ...g process It provides a 7 bit address If the ADEXT bit is set AD 10 8 in Control Register 2 participates in the address matching process It extends the I2C primary slave address to a 10 bit address Ad...

Page 867: ...and be able to receive a new START condition within the timeframe of TTIMEOUT MAX SMBus defines a clock low timeout TTIMEOUT of 35 ms specifies TLOW SEXT as the cumulative clock low extend time for a...

Page 868: ...ut intervals TLOW SEXT and TLOW MEXT When in master mode the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is defined as ST...

Page 869: ...to acknowledge its own address as a mechanism to detect the presence of a removable device such as a battery or docking station on the bus In addition to indicating a slave device busy condition SMBus...

Page 870: ...ed calling address IAAS IICIF IICIE Arbitration lost ARBL IICIF IICIE I2C bus stop detection STOPF IICIF IICIE STOPIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SDA low timeout SHTF2 IICIF...

Page 871: ...tion lost interrupt when it loses the data arbitration process and the ARBL bit in the Status Register is set Arbitration is lost in the following circumstances 1 SDA is sampled as low when the master...

Page 872: ...e programmer must specify the size of the glitch in terms of I2C module clock cycles for the filter to absorb and not pass SCL SDA external signals DFF Noise suppress circuits SCL SDA internal signals...

Page 873: ...erefore the DMA must be disabled before the last byte s transfer NOTE In 10 bit address mode transmission the addresses to send occupy 2 3 bytes During this transfer period the DMA must be disabled be...

Page 874: ...arget slave the LSB of this byte determines whether the communication is master receive or transmit The routine shown in the following figure encompasses both master and slave I2C operations For slave...

Page 875: ...tes 1 If general call is enabled check to determine if the received address is a general call address 0x00 If the received address is a general call address the general call must be handled by user so...

Page 876: ...to Data reg Clear IICIF Notes 1 If general call or SIICAEN is enabled check to determine if the received address is a general call address 0x00 or an SMBus device default address In either case they...

Page 877: ...Initialization application information MKW01Z128 MCU Reference Manual Rev 3 04 2016 746 Freescale Semiconductor Inc...

Page 878: ...ion chapter changes Added a note with respect to EXTRG_IN peripheral that it is unavailable on MKW01 in Table 1 1 Module to module interconnects Updated input signal of AD5a channel from Reserved to A...

Page 879: ...t changes A 8 PORT changes In Pin Control Register PCRn added additional details to Interrupt Configuration field IRQC description A 9 SIM changes No substantial content changes A 10 SMC changes No su...

Page 880: ...nges A 15 MCM changes No substantial content changes A 16 MTB configuration changes No substantial content changes A 17 Crossbar switch module changes No substantial content changes A 18 AIPS module c...

Page 881: ...es A 21 MCG changes Updated the bitfield access of ATMF and LOCS0 in the MCG_SC register A 22 OSC changes No substantial content changes A 23 FMC changes No substantial content changes A 24 FTFA chang...

Page 882: ...d 1 hour to 1 minute in Example configuration for chained timers Added information about register access level at the end of each register description A 30 LPTMR changes No substantial content changes...

Page 883: ...34 UART chapter changes No substantial content changes A 35 GPIO changes Updated Features A 36 Touch sense input chapter changes No substantial content changes UART0 chapter changes MKW01Z128 MCU Ref...

Page 884: ...ncidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operati...

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