NXP Semiconductors MKW01Z128, Reference Manual, Page: 163 / 884

1.3.1 ARM Cortex-M0+ core configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by ARM and can be found at
arm.com
.
ARM Cortex-M0+
Core
Debug Interrupts
Crossbar
switch
Figure 1-1. Core configuration
Table 1-3. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M0+ core,
r0p0
ARM Cortex-M0+ Technical Reference Manual, r0p0
System memory map System memory map
Clocking Clock distribution
Power management Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
Debug Serial wire debug
(SWD)
Debug
Interrupts Nested vectored
interrupt controller
(NVIC)
NVIC
Miscellaneous control
module (MCM)
MCM
1.3.1.1 ARM Cortex M0+ core
The ARM Cortex M0+ parameter settings are as follows:
Table 1-4. ARM Cortex-M0+ parameter settings
Parameter Verilog name Value Description
Arch Clock Gating ACG 1 = Present Implements architectural clock gating
DAP Slave Port Support AHBSLV 1 Supports any AHB debug access port (like the
CM4 DAP)
Table continues on the next page...
Core modules
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
32 Freescale Semiconductor, Inc.