NXP Semiconductors MKW01Z128, Reference Manual

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If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow (when the zero is loaded into the TPM counter), and it is forced low at the
channel (n) match (TPM counter = CnV) (see the following figure).
TOF bit
CHnF bit
CNT
channel (n) output
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0 1 2 3 4 5 6 7 8 0 1 2
...
previous value
Figure 27-10. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow (when zero is loaded into the TPM counter), and it is forced high at the channel
(n) match (TPM counter = CnV) (see the following figure).
TOF bit
CHnF bit
CNT
channel (n) output
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0 1 2 3 4 5 6 7 8 0 1 2
...
previous value
Figure 27-11. EPWM signal with ELSnB:ELSnA = X:1
If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal. If (CnV
> MOD), then the channel (n) output is a 100% duty cycle EPWM signal and CHnF bit is
not set since there is never a channel (n) match. Therefore, MOD must be less than
0xFFFF in order to get a 100% duty cycle EPWM signal.
27.4.7 Center-Aligned PWM (CPWM) Mode
The center-aligned mode is selected when (CPWMS = 1) and (MSnB:MSnA = 1:0).
The CPWM pulse width (duty cycle) is determined by 2 × CnV and the period is
determined by 2 × MOD (see the following figure). MOD must be kept in the range of
0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
In the CPWM mode, the TPM counter counts up until it reaches MOD and then counts
down until it reaches zero.
Chapter 27 Timer/PWM Module (TPM)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 535