NXP Semiconductors MKW01Z128, Reference Manual, Page: 67 / 884

Sub 1 GHz Transceiver Architecture Description
MKW01xxRM Reference Manual, Rev. 3, 04/2016
5-12 Freescale Semiconductor, Inc.
5.7.2.1 RssiThreshold Setting
For correct operation of the AGC, RssiThreshold in RegRssiThresh must be set to the sensitivity of the
receiver. The receiver will remain in WAIT mode until RssiThreshold is exceeded.
NOTE
When AFC is enabled and performed automatically at the receiver startup,
the channel filter is used by the receiver during the AFC and the AGC is
RxBwAfc instead of the standard RxBw setting. This may impact the
sensitivity of the receiver, and the setting of RssiThreshold accordingly.
5.7.2.2 AGC Reference
The AGC reference level is automatically computed in the transceiver according to:
AGC Reference [dBm] = -174 + NF + De10*log(2*RxBw) + FadingMargin [dBm]
With:
• NF = 7dB : LNA’s Noise Figure at maximum gain
• DemodSnr = 8 dB : SNR needed by the demodulator
• RxBw : Single sideband channel filter bandwidth
• FadingMargin = 5 dB : Fading margin
5.7.3 Continuous-Time DAGC
In addition to the automatic gain control described in Section 5.7.2, “Automatic Gain Control” , the
transceiver is capable of continuously adjusting its gain in the digital domain, after the analog to digital
conversion has occurred. This feature, named DAGC, is fully transparent to the end user. The digital gain
adjustment is repeated every 2 bits, and has the following benefits:
• Fully transparent to the end user
• Improves the fading margin of the receiver during the reception of a packet, even if the gain of the
LNA is frozen
• Improves the receiver robustness in fast fading signal conditions, by quickly adjusting the receiver
gain (every 2 bits)
• Works in Continuous, Packet, and unlimited length Packet modes
The DAGC is enabled by setting RegTestDagc to 0x20 for low modulation index systems (i.e. when
AfcLowBetaOn=1 ) and 0x30 for other systems. It is recommended to always enable the DAGC.
5.7.4 Quadrature Mixer - ADCs - Decimators
The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter
(ADC) of the receiver section. This block is designed to translate the spectrum of the input RF signal to
baseband, and offer both high IIP2 and IIP3 responses.