NXP Semiconductors MKW01Z128, Reference Manual

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LLWU_FILT1 field descriptions (continued)
Field Description
Selects 1 out of the 16 wakeup pins to be muxed into the filter.
0000 Select LLWU_P0 for filter
... ...
1111 Select LLWU_P15 for filter
11.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)
LLWU_FILT2 is a control and status register that is used to enable/disable the digital
filter 2 features for an external pin.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 9h offset = 4007_C009h
Bit 7 6 5 4 3 2 1 0
Read FILTF
FILTE
0
FILTSEL
Write w1c
Reset 0 0 0 0 0 0 0 0
LLWU_FILT2 field descriptions
Field Description
7
FILTF
Filter Detect Flag
Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage
power mode. To clear the flag write a one to FILTF.
0 Pin Filter 2 was not a wakeup source
1 Pin Filter 2 was a wakeup source
6–5
FILTE
Digital Filter On External Pin
Controls the digital filter options for the external pin detect.
00 Filter disabled
01 Filter posedge detect enabled
10 Filter negedge detect enabled
11 Filter any edge detect enabled
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FILTSEL Filter Pin Select
Table continues on the next page...
Memory map/register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
220 Freescale Semiconductor, Inc.