NXP Semiconductors MKW01Z128, Reference Manual, Page: 332 / 884

NOTE
This register is reset on Chip Reset Not VLLS and by reset
types that trigger Chip Reset not VLLS. See the Reset section
details for more information.
Address: 4007_D000h base + 2h offset = 4007_D002h
Bit 7 6 5 4 3 2 1 0
Read 0
VLPO Reserved BGEN
ACKISO REGONS
Reserved BGBE
Write w1c
Reset 0 0 1 0 0 1 0 0
PMC_REGSC field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
VLPO
VLPx Option
When used in conjunction with BGEN, this bit allows additional clock sources and higher frequency
operation (at the cost of higher power) to be selected during VLPx modes.
0 Operating frequencies and MCG clocking modes are restricted during VLPx modes as listed in the
Power Management chapter.
1 If BGEN is also set, operating frequencies and MCG clocking modes are unrestricted during VLPx
modes. Note that flash access frequency is still restricted however.
5
Reserved
This field is reserved.
4
BGEN
Bandgap Enable In VLPx Operation
BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and
VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of
operation, set BGEN to continue to enable the bandgap operation.
NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid
excess power consumption.
0 Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
1 Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
3
ACKISO
Acknowledge Isolation
Reading this field indicates whether certain peripherals and the I/O pads are in a latched state as a result
of having been in a VLLS mode. Writing 1 to this field when it is set releases the I/O pads and certain
peripherals to their normal run mode state.
NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing
ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to
avoid any LLWU flag from being falsely set when ACKISO is cleared.
0 Peripherals and I/O pads are in normal run state.
1 Certain peripherals and I/O pads are in an isolated and latched state.
2
REGONS
Regulator In Run Regulation Status
This read-only field provides the current status of the internal voltage regulator.
Table continues on the next page...
Chapter 10 Power Management Controller (PMC)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 201