NXP Semiconductors MKW01Z128, Reference Manual

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32.2.2 UART Baud Rate Register Low (UARTx_BDL)
This register, along with UART_BDH, control the prescale divisor for UART baud rate
generation. The 13-bit baud rate setting [SBR12:SBR0] can only be updated when the
transmitter and receiver are both disabled.
UART_BDL is reset to a non-zero value, so after reset the baud rate generator remains
disabled until the first time the receiver or transmitter is enabled; that is, UART_C2[RE]
or UART_C2[TE] bits are written to 1.
Address: Base a 1h offset
Bit 7 6 5 4 3 2 1 0
Read
SBR
Write
Reset 0 0 0 0 0 1 0 0
UARTx_BDL field descriptions
Field Description
SBR Baud Rate Modulo Divisor
These 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the baud
rate generator. When BR is 1 - 8191, the baud rate equals baud clock/((OSR+1) × BR).
32.2.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system. This
register should only be altered when the transmitter and receiver are both disabled.
Address: Base a 2h offset
Bit 7 6 5 4 3 2 1 0
Read
LOOPS DOZEEN RSRC M WAKE ILT PE PT
Write
Reset 0 0 0 0 0 0 0 0
UARTx_C1 field descriptions
Field Description
7
LOOPS
Loop Mode Select
Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the
transmitter output is internally connected to the receiver input.
Table continues on the next page...
Register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
624 Freescale Semiconductor, Inc.