NXP Semiconductors MKW01Z128, Reference Manual, Page: 226 / 884

Table 3-1. Clock summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
or VLLS0 and oscillator
not in external clock
mode.
RTC_CLKOUT RTC 1Hz,
OSCERCLK
RTC 1Hz,
OSCERCLK
RTC 1Hz,
OSCERCLK
Clock is disabled in LLS
and VLLSx modes
LPO 1 kHz 1 kHz PMC in VLLS0
TPM clock Up to 48 MHz Up to 8 MHz MCGIRCLK,
MCGPLLCLK/2,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[TPMSRC
]=00 or selected clock
source disabled.
UART0 clock Up to 48 MHz Up to 8 MHz MCGIRCLK,
MCGPLLCLK/2,
MCGFLLCLK, or
OSCERCLK
SIM_SOPT2[UART0SR
C]=00 or selected clock
source disabled.
1. If in BLPI mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency
needs to be limited to 800 kHz if executing from flash.
3.5 Internal clocking requirements
The clock dividers are programmed via the CLKDIV registers of the SIM module.
The following requirements must be met when configuring the clocks for this device:
• The core, platform, and system clock are programmable from a divide-by-1 through
divide-by-16 setting. The core, platform, and system clock frequencies must be 48
MHz or slower.
• The frequency of bus clock and flash clock is divided by the system clock and is
programmable from a divide-by-1 through divide-by-8 setting. The bus clock and
flash clock must be programmed to 24 MHz or slower.
The following is a common clock configuration for this device:
Clock Frequency
Core clock 48 MHz
Platform clock 48 MHz
System clock 48 MHz
Bus clock 24 MHz
Flash clock 24 MHz
Chapter 3 Clock Distribution
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 95