NXP Semiconductors MKW01Z128, Reference Manual, Page: 214 / 884

2.3.1 Alternate non-volatile IRC user trim description
The following non-volatile locations (4 bytes) are reserved for custom IRC user trim
supported by some development tools. An alternate IRC trim to the factory loaded trim
can be stored at this location. To override the factory trim, the user software must load
new values into the MCG trim registers.
Non-volatile byte address Alternate IRC Trim Value
0x0000_03FC Reserved
0x0000_03FD Reserved
0x0000_03FE (bit 0) SCFTRIM
0x0000_03FE (bit 4:1) FCTRIM
0x0000_03FE (bit 6) FCFTRIM
0x0000_03FF SCTRIM
2.4 SRAM memory map
The on-chip RAM is split between SRAM_L and SRAM_U. The RAM is also
implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in
the memory map.
See SRAM ranges for details.
Access to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on
the device causes the bus cycle to be terminated with an error followed by the appropriate
response in the requesting bus master.
2.5 Bit Manipulation Engine
The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify-
write memory operations to the peripheral address space.
By combining the basic load and store instruction support in the Cortex-M instruction set
architecture with the concept of decorated storage provided by the BME, the resulting
implementation provides a robust and efficient read-modify-write capability to this class
of ultra low-end microcontrollers. See the
Bit Manipulation Engine Block Guide (BME)
for a detailed description of BME functionality.
Chapter 2 Memory Map
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 83