NXP Semiconductors MKW01Z128, Reference Manual

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1.6.3 SRAM configuration
This section summarizes how the module has been configured in the chip.
SRAM upper
Transfers
Cortex-M0+
core
switch
SRAM lower
crossbar
SRAM
controller
Figure 1-19. SRAM configuration
Table 1-29. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map — System memory map
Clocking — Clock distribution
ARM Cortex-M0+ core — ARM Cortex-M0+ core
1.6.3.1 SRAM sizes
This device contains SRAM which could be accessed by bus masters through the cross-
bar switch. The amount of SRAM for the device covered in this document is shown in the
following table.
Table 1-30. KW01xxx SRAM memory size
Device SRAM (KB)
MKW01xxx 16
1.6.3.2 SRAM ranges
The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated
to SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 57