NXP Semiconductors MKW01Z128, Reference Manual

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Chapter 2
Memory Map
2.1 Introduction
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space.
This chapter describes the memory and peripheral locations within that memory space.
2.2 System memory map
The table found here shows the high-level device memory map.
Table 2-1. System memory map
System 32-bit address range Destination slave Access
0x0000_0000–0x07FF_FFFF
1
Program flash and read-only data
(Includes exception vectors in first 196 bytes)
All masters
0x0800_0000–0x1FFF_DFFF Reserved —
0x1FFF_E000–0x1FFF_FFFF SRAM_L: Lower SRAM All masters
0x2000_0000–0x2000_5FFF
2
SRAM_U: Upper SRAM All masters
0x2000_6000–0x3FFF_FFFF Reserved –
0x4000_0000–0x4007_FFFF AIPS Peripherals Cortex-M0+ core &
DMA
0x4008_0000–0x400F_EFFF Reserved –
0x400F_F000–0x400F_FFFF General-purpose input/output (GPIO) Cortex-M0+ core &
DMA
0x4010_0000–0x43FF_FFFF Reserved –
0x4400_0000–0x5FFF_FFFF Bit Manipulation Engine (BME) access to AIPS Peripherals for
slots 0-127
3
Cortex-M0+ core
0x6000_0000–0xDFFF_FFFF Reserved –
0xE000_0000–0xE00F_FFFF Private Peripherals Cortex-M0+ core
0xE010_0000–0xEFFF_FFFF Reserved –
Table continues on the next page...
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 81