NXP Semiconductors MKW01Z128, Reference Manual, Page: 789 / 884

UARTx_C3 field descriptions (continued)
Field Description
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
4
TXINV
Transmit Data Inversion
Setting this field reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
0 Transmit data not inverted.
1 Transmit data inverted.
3
ORIE
Overrun Interrupt Enable
Enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled; use polling.
1 Hardware interrupt requested when OR is set.
2
NEIE
Noise Error Interrupt Enable
Enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled; use polling).
1 Hardware interrupt requested when NF is set.
1
FEIE
Framing Error Interrupt Enable
Enables the framing error flag (FE) to generate hardware interrupt requests.
0 FE interrupts disabled; use polling).
1 Hardware interrupt requested when FE is set.
0
PEIE
Parity Error Interrupt Enable
Enables the parity error flag (PF) to generate hardware interrupt requests.
0 PF interrupts disabled; use polling).
1 Hardware interrupt requested when PF is set.
33.3.8 UART Data Register (UARTx_D)
This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for the UART
status flags.
Address: Base a 7h offset
Bit 7 6 5 4 3 2 1 0
Read
R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0
Write
Reset
0 0 0 0 0 0 0 0
Register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
658 Freescale Semiconductor, Inc.