NXP Semiconductors MKW01Z128, Reference Manual

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Transceiver Operating Modes
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 6-7
Upon detection of a valid packet, the sequencing is altered, as shown below:
Figure 6-6. Listen Mode Sequence (wanted signal is received)
Listen mode can be disabled by writing ListenOn to 0.
6.3.4 RC Timer Accuracy
All timings of the Listen Mode rely on the accuracy of the internal low-power RC oscillator. This oscillator
is automatically calibrated at the device power-up, and it is a user-transparent process.
For applications enduring large temperature variations, and for which the power supply is never removed,
RC calibration can be performed upon user request.
RcCalStart in RegOsc1 can be used to trigger this
calibration, and the flag RcCalDone will be set automatically when the calibration is over.
6.4 AutoModes
Automatic modes of packet handler can be enabled by configuring the related parameters in
RegAutoModes . The intermediate mode of the chip is called IntermediateMode and the enter and exit
conditions to/from this intermediate mode can be configured through the parameters EnterCondition &
ExitCondition . The enter and exit conditions cannot be used independently of each other i.e. both should
be enabled at the same time.
01
Chip stays in RX mode until PayloadReady or Timeout interrupt occurs. It then goes to the mode defined
by Mode . Listen mode stops and must be disabled.
10
Chip stays in RX mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle
state. FIFO content is lost at next RX wakeup.
Table 6-4. End of Listen Cycle Actions
PayloadReady
ListenCriteria
passed
Listen Mode
Idle Rx
Listen Mode
Listen Mode
Idle
Rx Mode
Idle
Rx Idle Rx
ListenEnd= 00
ListenEnd= 01
ListenEnd= 10