NXP Semiconductors MKW01Z128, Reference Manual

Page: 117 / 884

Transceiver Digital Control and Communications
MKW01xxRM Reference Manual, Rev. 3, 04/2016
7-30 Freescale Semiconductor, Inc.
RegIrqFlags1
(0x27) 7 ModeReady r 1 Set when the operation mode requested in
Mode , is ready
- Sleep: Entering Sleep mode
- Standby: XO is running
- FS: PLL is locked
- RX: RSSI sampling starts
- TX: PA ramp-up completed
Cleared when changing operating mode.
6 RxReady r 0 Set in RX mode, after RSSI, AGC and AFC.
Cleared when leaving RX.
5 TxReady r 0 Set in TX mode, after PA ramp-up.
Cleared when leaving TX.
4 PllLock r 0 Set (in FS, RX or TX) when the PLL is locked.
Cleared when it is not.
3 Rssi rwc 0 Set in RX when the RssiValue exceeds
RssiThreshold.
Cleared when leaving RX.
2 Timeout r 0 Set when a timeout occurs (see
TimeoutRxStart and TimeoutRssiThresh )
Cleared when leaving RX or FIFO is emptied.
1 AutoMode r 0 Set when entering Intermediate mode.
Cleared when exiting Intermediate mode.
Please note that in Sleep mode a small delay
can be observed between
AutoMode interrupt
and the corresponding enter/exit condition.
0 SyncAddressMatch r/rwc 0 Set when Sync and Address (if enabled) are
detected.
Cleared when leaving RX or FIFO is emptied.
This bit is read only in Packet mode, rwc in
Continuous mode
Table 7-8. IRQ and Pin Mapping Registers (continued)