NXP Semiconductors MKW01Z128, Reference Manual

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System Considerations
MKW01xxRM Reference Manual, Rev. 3, 04/2016
4-4 Freescale Semiconductor, Inc.
4.3.2 System Reset
The MKW01Z128 system does not have a master input that resets the entire SiP:
• The MCU reset input is pin 33, RESET_b — use of this pin as an external reset is optional, and the
MCU has a separate power-on reset (POR).
• The transceiver has an independent reset pin (RESET), pin 48 — this signal is typically connected
to an MCU GPIO to provide total software control of the transceiver
NOTE
It is recommended that the MCU be connected to the transceiver reset via
an MCU GPIO pin to provide best overall hardware control.
4.3.2.1 MCU Reset pin (pin 33)
On this device, RESET is a dedicated input pin for which filtering can be enabled. This pin is open drain
and has an internal pullup device. This pin can be disabled or configured as a GPIO (PTA20). Asserting
RESET (low) wakes the device from any mode. During a pin reset, the RCM's SRS0 PIN bit is set. The
MCU's Low Voltage Detect (LVD) can also generate a reset.
4.3.2.2 Transceiver Reset
The transceiver can be reset via two means:
• A power-on reset (POR) of the MKW01Z128 transceiver is triggered when VDD is applied to
VBAT1 and VBAT2.
• A hardware reset can be issued by controlling Pin 48 (transceiver RESET).
4.3.2.2.1 Transceiver POR
Similar to the MCU, a transceiver POR is internally generated when power is applied to VDD. See
Figure 4-2 for the transceiver POR timing diagram.
• The transceiver hardware RESET pin is bidirectional and is first driven to high as the result of the
POR.
• The RESET signal is then driven low, and the application must wait for 10 ms from the end of the
POR cycle before commencing communications over the SPI bus.
• RESET should be left floating during the POR sequence.