NXP Semiconductors MKW01Z128, Reference Manual

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MKW01Z128 Transceiver - MCU SPI Interface
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 8-5
Figure 8-3. Transceiver SPI Read Single Access Timing Diagram
The SPI Bus timing is determined by the transceiver specification as given in Table 8-1.
NOTE
For the onboard MCU, the bus clock to the SPI module is always ½ the CPU
clock, and in turn, the maximum SPI clock baud rate is ½ the peripheral
clock. The default bus clock rate for some versions of Freescale supplied
software is 32 MHz which in turn provides an 8 MHz SPI baud rate.
Table 8-1. Transceiver SPI Timing Specifications
Parameter Min Typ Max Unit
SPSCK period 100 ns
Pulse width, SPSCK low 50 ns
Pulse width, SPSCK high 50 ns
Setup time, SS low to rising SPSCK 30 ns
Hold time, from falling SPSCK to SS rising edge 60 ns
Setup time, MOSI valid to rising SPSCK 30 ns
Hold time, MOSI valid from rising SPSCK 60 ns
SS high time between accesses 20 ns