NXP Semiconductors MKW01Z128, Reference Manual

Page: 757 / 884

32.2.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base a 3h offset
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C2 field descriptions
Field Description
7
TIE
Transmit Interrupt Enable for TDRE
0 Hardware interrupts from TDRE disabled; use polling.
1 Hardware interrupt requested when TDRE flag is 1.
6
TCIE
Transmission Complete Interrupt Enable for TC
0 Hardware interrupts from TC disabled; use polling.
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable for RDRF
0 Hardware interrupts from RDRF disabled; use polling.
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable for IDLE
0 Hardware interrupts from IDLE disabled; use polling.
1 Hardware interrupt requested when IDLE flag is 1.
3
TE
Transmitter Enable
TE must be 1 to use the UART transmitter. When TE is set, the UART forces the UART_TX pin to act as
an output for the UART system.
When the UART is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the
direction of traffic on the single UART communication line ( UART_TX pin).
TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress.
When TE is written to 0, the transmitter keeps control of the port UART_TX pin until any data, queued idle,
or queued break character finishes transmitting before allowing the pin to tristate.
0 Transmitter disabled.
1 Transmitter enabled.
2
RE
Receiver Enable
When the UART receiver is off or LOOPS is set, the UART_RX pin is not used by the UART .
When RE is written to 0, the receiver finishes receiving the current character (if any).
0 Receiver disabled.
1 Receiver enabled.
1
RWU
Receiver Wakeup Control
Table continues on the next page...
Register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
626 Freescale Semiconductor, Inc.