NXP Semiconductors MKW01Z128, Reference Manual, Page: 662 / 884

0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4
TOF bit
set TOF bit set TOF bit
period of counting = 2 x MOD x period of timer module counter clock
MOD = 0x0004
period of timer module counter clock
Timer module counter
Figure 27-4. Example of up-down counting
27.4.3.3 Counter Reset
Any write to CNT resets the TPM counter and the channel outputs to their initial values
(except for channels in output compare mode).
27.4.3.4 Global time base (GTB)
The global time base (GTB) is a TPM function that allows multiple TPM modules to
share the same timebase. When the global time base is enabled (CONF[GTBEEN] = 1),
the local TPM channels use the counter value, counter enable and overflow indication
from the TPM generating the global time base. If the local TPM counter is not generating
the global time base, then it can be used as an independent counter or pulse accumulator.
27.4.3.5 Counter trigger
The TPM counter can be configured to start, stop or reset in response to a hardware
trigger input. The trigger input is synchronized to the asynchronous counter clock, so
there is a 3 counter clock delay between the trigger assertion and the counter responding.
• When (CSOT = 1), the counter will not start incrementing until a rising edge is
detected on the trigger input.
• When (CSOO= 1), the counter will stop incrementing whenever the TOF flag is set.
The counter does not increment again unless it is disabled, or if CSOT = 1 and a
rising edge is detected on the trigger input.
• When (CROT= 1), the counter will reset to zero as if an overflow occurred whenever
a rising edge is detected on the trigger input.
Chapter 27 Timer/PWM Module (TPM)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 531