NXP Semiconductors MKW01Z128, Reference Manual, Page: 162 / 884

Table 1-1. Module-to-module interconnects (continued)
Peripheral Signal — to
Peripheral
Use Case Control Comment
LPTMR Hardware
trigger
to TSI TSI triggering TSI selects HW trigger —
UART0 UART0_TX to Modulated by
TPM1 CH0
UART
modulation
SIM_SOPT5[UART0TXSRC]
UART0 UART0_TX to Modulated by
TPM2 CH0
UART
modulation
SIM_SOPT5[UART0TXSRC]
UART1 UART1_TX to Modulated by
TPM1 CH0
UART
modulation
SIM_SOPT5[UART1TXSRC]
UART1 UART1_TX to Modulated by
TPM2 CH0
UART
modulation
SIM_SOPT5[UART1TXSRC]
PIT TIF0 to DAC Advance
DAC FIFO
DAC HWTRG Select —
PIT TIF0 to DMA CH0 DMA HW
Trigger
DMA MUX register option —
PIT TIF1 to DMA CH1 DMA HW
Trigger
DMA MUX register option —
1.2.2 Analog reference options
Several analog blocks have selectable reference voltages as shown in Table 1-2 . These
options allow analog peripherals to share or have separate analog references. Care should
be taken when selecting analog references to avoid cross talk noise.
Table 1-2. Analog reference options
Module Reference option Comment/ Reference selection
16-bit SAR ADC 1 - VREFH
2 - VDDA
3 - Reserved
Selected by ADCx_SC2[REFSEL]
12-bit DAC 1 - VREFH
2 - VDDA
1
Selected by DACx_C0[DACRFS] bit
CMP with 6-bit DAC Vin1 - VREFH
Vin2 - VDD
Selected by CMPx_DACCR[VRSEL]
1. Use this option for the best ADC operation.
1.3 Core modules
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 31