NXP Semiconductors MKW01Z128, Reference Manual

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SCL2
Start Counting High Period
Internal Counter Reset
SCL1
SCL
Delay
Figure 36-3. I2C clock synchronization
36.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. A
slave device may hold SCL low after completing a single byte transfer (9 bits). In this
case, it halts the bus clock and forces the master clock into wait states until the slave
releases SCL.
36.4.1.9 Clock stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of
a transfer. After the master drives SCL low, a slave can drive SCL low for the required
period and then release it. If the slave's SCL low period is greater than the master's SCL
low period, the resulting SCL bus signal's low period is stretched. In other words, the
SCL bus signal's low period is increased to be the same length as the slave's SCL low
period.
36.4.1.10 I2C divider and hold values
NOTE
For some cases on some devices, the SCL divider value may
vary by ±2 or ±4 when ICR's value ranges from 00h to 0Fh.
These potentially varying SCL divider values are highlighted in
the following table. For the actual SCL divider values for your
device, see the chip-specific details about the I2C module.
Functional description
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
732 Freescale Semiconductor, Inc.