NXP Semiconductors MKW01Z128, Reference Manual, Page: 652 / 884

TPMx_MOD field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
MOD Modulo value
This field must be written with single 16-bit or 32-bit access.
27.3.4 Channel (n) Status and Control (TPMx_CnSC)
CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function. When switching from one
channel mode to a different channel mode, the channel must first be disabled and this
must be acknowledged in the TPM counter clock domain.
Table 27-2. Mode, Edge, and Level Selection
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X 00 00 None Channel disabled
X 01 00 Software compare Pin not used for TPM
0 00 01 Input capture Capture on Rising Edge
Only
10 Capture on Falling
Edge Only
11 Capture on Rising or
Falling Edge
01 01 Output compare Toggle Output on
match
10 Clear Output on match
11 Set Output on match
10 10 Edge-aligned PWM High-true pulses (clear
Output on match, set
Output on reload)
X1 Low-true pulses (set
Output on match, clear
Output on reload)
11 10 Output compare Pulse Output low on
match
01 Pulse Output high on
match
1 10 10 Center-aligned PWM High-true pulses (clear
Output on match-up,
set Output on match-
down)
Table continues on the next page...
Chapter 27 Timer/PWM Module (TPM)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 521