NXP Semiconductors MKW01Z128, Reference Manual

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Table 5-2. Module operation in low power modes (continued)
Modules VLPR VLPW Stop VLPS LLS VLLSx
GPIO FF
IOPORT write
only in CPO
FF static output,
wakeup input
FF in PSTOP2
static output,
wakeup input
static, pins
latched
OFF, pins
latched
TSI FF
Async operation
in CPO
Async
operation
7
Async
operation
7
FF in PSTOP2
Async
operation
7
Async operation Async
operation
7
1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be
enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a
transition to occur to the LLWU.
2. Since LPO clock source is disabled, filters will be bypassed during VLLS0.
3. STOPCTRL[PORPO] in the SMC module controls this option.
4. LPO clock source is not available in VLLS0. Also, to use system OSC in VLLS0 it must be configured for bypass (external
clock) operation. Pulse counting is available in all modes.
5. In VLLS0 the only clocking option is from RTC_CLKIN.
6. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS
or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered
modes of operation are not available while in Stop, VLPS, LLS, or VLLSx modes.
7. TSI wake-up from all low-power modes is limited to a single selectable pin.
Chapter 5 Power Management
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 123