NXP Semiconductors MKW01Z128, Reference Manual

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x+3
x+2
x+1
x
4c.v_wxyz
next
next
next
orig_1bit
400v_wxyz
400v_wxyz next
next
next
rdata + 1bit
rdata
4c.v_wxyz
rdata + 1bit
CYCLE RULER
hclk
BME AHB Input Bus
mx_haddr
mx_hattr
mx_hwrite
mx_hwdata
mx_hrdata
mx_hready
BME AHB Output Bus
sx_haddr
sx_hattr
sx_hwrite
sx_hwdata
sx_hrdata
sx_hready
BME Datapath
control_state_dp1
control_state_dp2
reg_addr_data_dp
Figure 13-7. Decorated load: load-and-set 1-bit field insert timing diagram
Decorated load-and-{set, clear} 1-bit operations follow the execution template shown in
the above figure: a 2-cycle read-modify-write operation:
1. Cycle x, first AHB address phase: Read from input bus is translated into a read
operation on the output bus with the actual memory address (with the decoration
removed) and then captured in a register
2. Cycle x+1, second AHB address phase: Write access with the registered (but actual)
memory address is output
3. Cycle x+1, first AHB data phase: The "original" 1-bit memory read data is captured
in a register, while the 1-bit field is set or clear based on the function defined by the
decoration with the modified data captured in a register; the input bus cycle is stalled
4. Cycle x+2, second AHB data phase: The selected original 1-bit is right-justified,
zero-filled and then driven onto the input read data bus, while the registered write
data is sourced onto the output write data bus
Functional description
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
240 Freescale Semiconductor, Inc.