SMC_PMCTRL field descriptions
Field
Description
7
Reserved
This field is reserved.
This bit is reserved for future expansion and should always be written zero.
6–5
RUNM
Run Mode Control
When written, causes entry into the selected run mode. Writes to this field are blocked if the protection
level has not been enabled using the PMPROT register.
NOTE: RUNM may be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM
should not be written back to RUN until PMSTAT=VLPR.
00
Normal Run mode (RUN)
01
Reserved
10
Very-Low-Power Run mode (VLPR)
11
Reserved
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
STOPA
Stop Aborted
When set, this read-only status bit indicates an interrupt occured during the previous stop mode entry
sequence, preventing the system from entering that mode. This field is cleared by reset or by hardware at
the beginning of any stop mode entry sequence and is set if the sequence was aborted.
0
The previous stop mode entry was successful.
1
The previous stop mode entry was aborted.
STOPM
Stop Mode Control
When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is
entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled
using the PMPROT register. After any system reset, this field is cleared by hardware on any successful
write to the PMPROT register.
NOTE: When set to VLLSx, the VLLSM field in the STOPCTRL register is used to further select the
particular VLLS submode which will be entered.
NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial
Stop mode if desired.
000
Normal Stop (STOP)
001
Reserved
010
Very-Low-Power Stop (VLPS)
011
Low-Leakage Stop (LLS)
100
Very-Low-Leakage Stop (VLLSx)
101
Reserved
110
Reseved
111
Reserved
9.3.3 Stop Control Register (SMC_STOPCTRL)
The STOPCTRL register provides various control bits allowing the user to fine tune
power consumption during the stop mode selected by the STOPM field.
Memory map and register descriptions
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
180
Freescale Semiconductor, Inc.
Summary of Contents for MKW01Z128
Page 7: ...MKW01xxRM Reference Manual Rev 3 04 2016 viii Freescale Semiconductor Inc...
Page 11: ...MKW01xxRM Reference Manual Rev 3 04 2016 xii Freescale Semiconductor Inc...
Page 133: ...MKW01Z128 MCU Reference Manual Rev 3 04 2016 2 Freescale Semiconductor Inc...
Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...
Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...
Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...