NXP Semiconductors MKW01Z128, Reference Manual

Page: 247 / 884

During Compute Operation, the AIPS peripheral space is disabled and attempted accesses
generate bus errors. The private peripheral space remains accessible during Compute
Operation, including the MCM, NVIC, IOPORT, and SysTick. Although access to the
GPIO registers via the IOPORT is supported, the GPIO Port Data Input registers do not
return valid data since clocks are disabled to the Port Control and Interrupt modules. By
writing to the GPIO Port Data Output registers, it is possible to control those GPIO ports
that are configured as output pins.
Compute Operation is controlled by the CPO register in the MCM (MCM_CPO), which
is only accessible to the CPU. Setting or clearing MCM_CPO[CPOREQ] initiates entry
or exit into Compute Operation. Compute Operation can also be configured to exit
automatically on detection of an interrupt, which is required in order to service most
interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and
any edge-sensitive interrupts can be serviced without exiting Compute Operation.
• When entering Compute Operation, the CPOACK status field in the CPO register of
MCM module (MCM_CPO[CPOACK]) indicates when entry has completed.
• When exiting Compute Operation in Run mode, MCM_CPO[CPOACK] negates
immediately.
• When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the
PMC to handle the change in power consumption. This delay means that
MCM_CPO[CPOACK] is polled to determine when the AIPS peripheral space can
be accessed without generating a bus error.
The DMA wake-up is also supported during Compute Operation and causes
MCM_CPO[CPOACK] to clear and the AIPS peripheral space to be accessible for the
duration of the DMA wakeup. At the completion of the DMA wake-up, the device
transitions back into Compute Operation.
5.2.4 Peripheral Doze
Several peripherals support a Peripheral Doze mode, where a register bit can be used to
disable the peripheral for the duration of a low-power mode. The flash memory can also
be placed in a low-power state during Peripheral Doze via a register bit in the SIM.
Peripheral Doze is defined to include all of the modes of operation listed below.
• The CPU is in Wait mode.
• The CPU is in Stop mode, including the entry sequence and for the duration of a
DMA wakeup.
• The CPU is in Compute Operation, including the entry sequence and for the duration
of a DMA wakeup.
Clocking modes
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
116 Freescale Semiconductor, Inc.