NXP Semiconductors MKW01Z128, Reference Manual

Page: 395 / 884

15.3.1.1 MTB Position Register (MTB_POSITION)
The MTB_POSITION register contains the Trace Write Address Pointer and Wrap fields.
This register can be modified by the explicit programming model writes. It is also
automatically updated by the MTB hardware when trace packets are being recorded.
The base address of the system RAM in the memory map dictates special consideration
for the placement of the MTB. Consider the following guidelines:
For the standard configuration where the size of the MTB is ≤ 25% of the total RAM
capacity, it is recommended the MTB be based at the address defined by the MTB_BASE
register. The read-only MTB_BASE register is defined by the expression (0x2000_0000 -
(RAM_Size/4)). For this configuration, the MTB_POSITION register is initialized to
MTB_BASE & 0x0000_7FF8.
If the size of the MTB is more than 25% but less than or equal to 50% of the total RAM
capacity, it is recommended the MTB be based at address 0x2000_0000. In this
configuration, the MTB_POSITION register is initialized to (0x2000_0000 &
0x0000_7FF8) = 0x0000_00000.
Following these two suggested placements provides a full-featured circular memory
buffer containing program trace packets.
In the unlikely event an even larger trace buffer is required, a write-once capacity of 75%
of the total RAM capacity can be based at address 0x2000_0000. The MTB_POSITION
register is initialized to (0x2000_0000 & 0x0000_7FF8) = 0x0000_0000. However, this
configuration cannot support operation as a circular queue and instead requires the use of
the MTB_FLOW[WATERMARK] capability to automatically disable tracing or halting
the processor as the number of packet writes approach the buffer capacity. See the
MTB_FLOW register description for more details.
Address: F000_0000h base + 0h offset = F000_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
POINTER
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
POINTER
WRAP
0
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* 0 0
Memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
264 Freescale Semiconductor, Inc.