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FTFA_FSTAT field descriptions (continued)
Field
Description
The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution
when CCIF=1 and before the next command has been launched. At some point during the execution of
"command-N+1," the previous result is discarded and any previous error is cleared.
23.3.3.2 Flash Configuration Register (FTFA_FCNFG)
This register provides information on the current functional state of the flash memory
module.
The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. The
unassigned bits read as noted and are not writable.
Address: 4002_0000h base + 1h offset = 4002_0001h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
FTFA_FCNFG field descriptions
Field
Description
7
CCIE
Command Complete Interrupt Enable
Controls interrupt generation when a flash command completes.
0
Command complete interrupt disabled
1
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF]
flag is set.
6
RDCOLLIE
Read Collision Error Interrupt Enable
Controls interrupt generation when a flash memory read collision error occurs.
0
Read collision error interrupt disabled
1
Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory
read collision error is detected (see the description of FSTAT[RDCOLERR]).
5
ERSAREQ
Erase All Request
Issues a request to the memory controller to execute the Erase All Blocks command and release security.
ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip
Configuration details on how to request this command.
ERSAREQ sets when an erase all request is triggered external to the flash memory module and CCIF is
set (no command is currently being executed). ERSAREQ is cleared by the flash memory module when
the operation completes.
0
No request or request complete
1
Request to:
1. run the Erase All Blocks command,
Table continues on the next page...
Chapter 23 Flash Memory Module (FTFA)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc.
395
Summary of Contents for MKW01Z128
Page 7: ...MKW01xxRM Reference Manual Rev 3 04 2016 viii Freescale Semiconductor Inc...
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Page 133: ...MKW01Z128 MCU Reference Manual Rev 3 04 2016 2 Freescale Semiconductor Inc...
Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...
Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...
Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...