NXP Semiconductors MKW01Z128, Reference Manual

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35.3.2 TSI DATA Register (TSIx_DATA)
Address: 4004_5000h base + 4h offset = 4004_5004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
TSICH
0
DMAEN
0 0
W
SWTS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TSICNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_DATA field descriptions
Field Description
31–28
TSICH
TSICH
These bits specify current channel to be measured. In hardware trigger mode (TSI_GENCS[STM] = 1), the
scan will not start until the hardware trigger occurs. In software trigger mode (TSI_GENCS[STM] = 0), the
scan starts immediately when TSI_DATA[SWTS] bit is written by 1.
0000 Channel 0.
0001 Channel 1.
0010 Channel 2.
0011 Channel 3.
0100 Channel 4.
0101 Channel 5.
0110 Channel 6.
0111 Channel 7.
1000 Channel 8.
1001 Channel 9.
1010 Channel 10.
1011 Channel 11.
1100 Channel 12.
1101 Channel 13.
Table continues on the next page...
Register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
694 Freescale Semiconductor, Inc.