NXP Semiconductors MKW01Z128, Reference Manual

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System Considerations
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 4-3
Figure 4-1. MKW01Z128 power supply connections
NOTE
Depending on the application, the VREFH high reference voltage for the
ADC module is commonly also tied to the VDD common supply and the
VREFL low reference voltage is tied to ground.
4.3 System functional interconnects
The MKW01Z128 comprises two separate devices in a single package. The MCU controls the transceiver
and there are connections between the devices for several functions.
• Some connections are provided on chip
• Additional external connections may also be used depending on the application needs.
— Transceiver reset
— Clock interconnect
— Additional transceiver status
— Enhanced packet performance
4.3.1 In-package Connections (SPI Channel and Status)
The internal (in-package) device connections are listed in Table 2-2 . These include:
• SPI communication channel - see Chapter 8, “MKW01Z128 Transceiver - MCU SPI Interface”
• Transceiver DIO0 and DIO1 outputs as status - these status outputs are used to manage the data
• flow and transceiver sequencer during radio packet mode operation. Enhanced performance can be
obtained by additionally connecting these pins externally to other GPIO pins described below.
43
100 nF
56
19
4
20
3
FLAG
VSS
VSSAD
MKW01
VBAT1
VBAT2
VR_DIG
VR_ANA
GND_PA2
GND_PA1
GND
35
45
44
38
40
36
100 nF
100 nF 100 nF
100 nF
55
FLAG
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDDA