NXP Semiconductors MKW01Z128, Reference Manual, Page: 496 / 884

4. Lastly, PBE mode transitions into PEE mode:
a. C1 = 0x10
• C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock
source.
b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to
feed MCGOUTCLK in the current clock mode.
• Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24,
MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz.
Chapter 20 Multipurpose Clock Generator (MCG)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 365