
Transceiver Digital Control and Communications
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc.
7-13
The transmission of packet data is initiated by the Packet Handler only if the chip is in TX mode and the
transmission condition defined by
TxStartCondition
is fulfilled. If transmission condition is not fulfilled
then the packet handler transmits a preamble sequence until the condition is met. This happens only if the
preamble length
0, otherwise it transmits a zero or one until the condition is met to transmit the packet
data.
The transmission condition itself is defined as:
•
if
TxStartCondition
= 1, the packet handler waits until the first byte is written into the FIFO, then
it starts sending the preamble followed by the sync word and user payload
•
If
TxStartCondition
= 0, the packet handler waits until the number of bytes written in the FIFO is
equal to the number defined in
RegFifoThresh
+ 1
•
If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then
the transmission of packet starts immediately on enabling TX
7.5.4
RX Processing (without AES)
In RX mode the packet handler extracts the user payload to the FIFO by performing the following
operations:
•
Receiving the preamble and stripping it off
•
Detecting the Sync word and stripping it off
•
Optional DC-free decoding of data
•
Optionally checking the address byte
•
Optionally checking CRC and reflecting the result on
CrcOk.
Only the payload (including optional address and length fields) is made available in the FIFO.
When the RX mode is enabled the demodulator receives the preamble followed by the detection of sync
word. If fixed length packet format is enabled then the number of bytes received as the payload is given
by the
PayloadLength
parameter.
In variable length mode the first byte received after the sync word is interpreted as the length of the
received packet. The internal length counter is initialized to this received length. The
PayloadLength
register is set to a value which is greater than the maximum expected length of the received packet. If the
received length is greater than the maximum length stored in
PayloadLength
register the packet is
discarded otherwise the complete packet is received.
If the address check is enabled then the second byte received in case of variable length and first byte in
case of fixed length is the address byte. If the address matches to the one in the
NodeAddress
field,
reception of the data continues otherwise it's stopped. The CRC check is performed if
CrcOn
= 1 and the
result is available in
CrcOk
indicating that the CRC was successful. An interrupt (
PayloadReady
) is also
generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can
also be read in Sleep/Standby mode.
If the CRC fails the
PayloadReady
interrupt is not generated and the FIFO is cleared. This function can be
overridden by setting
CrcAutoClearOff
= 1, forcing the availability of
PayloadReady
interrupt and the
payload in the FIFO even if the CRC fails.
Summary of Contents for MKW01Z128
Page 7: ...MKW01xxRM Reference Manual Rev 3 04 2016 viii Freescale Semiconductor Inc...
Page 11: ...MKW01xxRM Reference Manual Rev 3 04 2016 xii Freescale Semiconductor Inc...
Page 133: ...MKW01Z128 MCU Reference Manual Rev 3 04 2016 2 Freescale Semiconductor Inc...
Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...
Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...
Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...